MCRR Move to System register from two general-purpose registers Move to System register from two general-purpose registers. This instruction copies the values of two general-purpose registers to a System register. The System register descriptions identify valid encodings for this instruction. Other encodings are UNDEFINED. For more information see About the AArch32 System register interface and General behavior of System registers. In an implementation that includes EL2, MCRR accesses to System registers can be trapped to Hyp mode, meaning that an attempt to execute an MCRR instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see EL2 configurable instruction enables, disables, and traps. Because of the range of possible traps to Hyp mode, the MCRR pseudocode does not show these possible traps. For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors. The possible values of { <coproc>, <opc1>, <CRm> } encode the entire System register encoding space. Not all of this space is allocated, and the System register descriptions identify the allocated encodings. For the permitted uses of these instructions, as described in this manual, <Rt2> transfers bits[63:32] of the selected System register, while <Rt> transfers bits[31:0]. It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) . != 1111 1 1 0 0 0 1 0 0 1 1 1 MCRR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <Rt2>, <CRm> let t : integer = UInt(Rt); let t2 : integer = UInt(Rt2); let cp : integer = if cp15 == '0' then 14 else 15; if t == 15 || t2 == 15 then UnpredictableProcedure(); end; // Armv8-A removes UNPREDICTABLE for R13 1 1 1 0 1 1 0 0 0 1 0 0 1 1 1 MCRR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <Rt2>, <CRm> let t : integer = UInt(Rt); let t2 : integer = UInt(Rt2); let cp : integer = if cp15 == '0' then 14 else 15; if t == 15 || t2 == 15 then UnpredictableProcedure(); end; // Armv8-A removes UNPREDICTABLE for R13 <c> See Standard assembler syntax fields. <q> See Standard assembler syntax fields. <coproc> Is the System register encoding space, cp15 <coproc> 0 p14 1 p15 <opc1> Is the opc1 parameter within the System register encoding space, in the range 0 to 15, encoded in the "opc1" field. <Rt> Is the first general-purpose register that is transferred into, encoded in the "Rt" field. <Rt2> Is the second general-purpose register that is transferred into, encoded in the "Rt2" field. <CRm> Is the CRm parameter within the System register encoding space, in the range c0 to c15, encoded in the "CRm" field. if ConditionPassed() then EncodingSpecificOperations(); AArch32_SysRegWrite64(cp, ThisInstr(), t, t2); end; 2026-03-26 20:27:25 2026-03_rel