MOV, MOVS (register)
Move (register)
Move (register) copies a value from a register to the destination
register.
If the destination register is not the PC, the MOVS variant of the
instruction updates the condition flags based on the result.
The field descriptions for <Rd> identify the encodings
where the PC is permitted as the destination register. If the
destination register is the PC:
The MOV variant of the instruction is a branch. In the T32 instruction set (encoding T1) this is a simple branch, and in the A32 instruction set it is an interworking branch, see Pseudocode description of operations on the AArch32 general-purpose registers and the PC.
The MOVS variant of the instruction performs an exception return without the use of the stack. In this case:
The PE branches to the address written to the PC, and restores PSTATE from SPSR_<current_mode>.
The PE checks SPSR_<current_mode> for an illegal return event. See Illegal return events from AArch32 state.
The instruction is UNDEFINED in Hyp mode.
The instruction is CONSTRAINED UNPREDICTABLE in User mode and System mode.
For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
This instruction is a data-independent-time instruction as described in About the DIT bit.
This instruction is used by the aliases
ASRS (immediate)
S == '1' && stype == '10'
op == '10' && !InITBlock()
ASR (immediate)
S == '0' && stype == '10'
op == '10' && InITBlock()
LSLS (immediate)
S == '1' && imm5 != '00000' && stype == '00'
op == '00' && imm5 != '00000' && !InITBlock()
(S == '1' && stype == '00' && !(imm3 == '000')) || (S == '1' && stype == '00' && !(imm2 == '00'))
LSL (immediate)
S == '0' && imm5 != '00000' && stype == '00'
op == '00' && imm5 != '00000' && InITBlock()
(S == '0' && stype == '00' && !(imm3 == '000')) || (S == '0' && stype == '00' && !(imm2 == '00'))
LSRS (immediate)
S == '1' && stype == '01'
op == '01' && !InITBlock()
LSR (immediate)
S == '0' && stype == '01'
op == '01' && InITBlock()
RORS (immediate)
S == '1' && imm5 != '00000' && stype == '11'
(S == '1' && stype == '11' && !(imm3 == '000')) || (S == '1' && stype == '11' && !(imm2 == '00'))
ROR (immediate)
S == '0' && imm5 != '00000' && stype == '11'
(S == '0' && stype == '11' && !(imm3 == '000')) || (S == '0' && stype == '11' && !(imm2 == '00'))
RRXS
S == '1' && imm5 == '00000' && stype == '11'
S == '1' && imm3 == '000' && imm2 == '00' && stype == '11'
RRX
S == '0' && imm5 == '00000' && stype == '11'
S == '0' && imm3 == '000' && imm2 == '00' && stype == '11'
See
below for details of when each alias is preferred.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
,
T2
and
T3
)
.
!= 1111
0
0
0
1
1
0
1
(0)
(0)
(0)
(0)
0
0
0
0
0
0
0
1
1
MOV{<c>}{<q>} <Rd>, <Rm>, RRX
0
MOV{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount>}
1
0
0
0
0
0
1
1
MOVS{<c>}{<q>} <Rd>, <Rm>, RRX
1
MOVS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount>}
let d : integer = UInt(Rd);
let m : integer = UInt(Rm);
let setflags : boolean = (S == '1');
let (shift_t, shift_n) : (SRType, integer) = DecodeImmShift(stype, imm5);
0
1
0
0
0
1
1
0
MOV{<c>}{<q>} <Rd>, <Rm>
let d : integer = UInt(D::Rd);
let m : integer = UInt(Rm);
let setflags : boolean = FALSE;
let shift_t : SRType = SRType_LSL;
let shift_n : integer = 0;
if d == 15 && InITBlock() && !LastInITBlock() then UnpredictableProcedure(); end;
0
0
0
!= 11
MOV<c>{<q>} <Rd>, <Rm> {, <shift> #<amount>}
MOVS{<q>} <Rd>, <Rm> {, <shift> #<amount>}
let d : integer = UInt(Rd);
let m : integer = UInt(Rm);
let setflags : boolean = !InITBlock();
let (shift_t, shift_n) : (SRType, integer) = DecodeImmShift(op, imm5);
if op == '00' && imm5 == '00000' && InITBlock() then UnpredictableProcedure(); end;
op == '00' && imm5 == '00000' && InITBlock()
The instruction executes as if it passed its condition code check.
The instruction executes as NOP, as if it failed its condition code check.
The instruction executes as MOV Rd, Rm.
1
1
1
0
1
0
1
0
0
1
0
1
1
1
1
(0)
0
0
0
0
0
0
1
1
MOV{<c>}{<q>} <Rd>, <Rm>, RRX
0
MOV{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount>}
MOV{<c>}.W <Rd>, <Rm> {, LSL #0}
MOV<c>.W <Rd>, <Rm> {, <shift> #<amount>}
1
0
0
0
0
0
1
1
MOVS{<c>}{<q>} <Rd>, <Rm>, RRX
1
MOVS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount>}
MOVS.W <Rd>, <Rm> {, <shift> #<amount>}
let d : integer = UInt(Rd);
let m : integer = UInt(Rm);
let setflags : boolean = (S == '1');
let (shift_t, shift_n) : (SRType, integer) = DecodeImmShift(stype, imm3::imm2);
// Armv8-A removes UNPREDICTABLE for R13
if d == 15 || m == 15 then UnpredictableProcedure(); end;
<c>
See Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Rd>
For the "A1 MOV, rotate right with extend", "A1 MOV, shift or rotate by value", "A1 MOVS, rotate right with extend", and "A1 MOVS, shift or rotate by value" variants: is the general-purpose destination register, encoded in the "Rd" field. If the PC is used:
For the MOV variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see Pseudocode description of operations on the AArch32 general-purpose registers and the PC. Arm deprecates use of the instruction if <Rn> is the PC.
For the MOVS variant, the instruction performs an exception return, that restores PSTATE from SPSR_<current_mode>. Arm deprecates use of the instruction if <Rn> is not the LR, or if the optional shift or RRX argument is specified.
<Rd>
For the "T1" variant: is the general-purpose destination register, encoded in the "D:Rd" field. If the PC is used:
The instruction causes a branch to the address moved to the PC. This is a simple branch, see Pseudocode description of operations on the AArch32 general-purpose registers and the PC.
The instruction must either be outside an IT block or the last instruction of an IT block.
<Rd>
For the "T2", "T3 MOV, rotate right with extend", "T3 MOV, shift or rotate by value", "T3 MOVS, rotate right with extend", and "T3 MOVS, shift or rotate by value" variants: is the general-purpose destination register, encoded in the "Rd" field.
<Rm>
For the "A1 MOV, rotate right with extend", "A1 MOV, shift or rotate by value", "A1 MOVS, rotate right with extend", "A1 MOVS, shift or rotate by value", and "T1" variants: is the general-purpose source register, encoded in the "Rm" field. The PC can be used. Arm deprecates use of the instruction if <Rd> is the PC.
<Rm>
For the "T2", "T3 MOV, rotate right with extend", "T3 MOV, shift or rotate by value", "T3 MOVS, rotate right with extend", and "T3 MOVS, shift or rotate by value" variants: is the general-purpose source register, encoded in the "Rm" field.
<shift>
For the "A1 MOV, shift or rotate by value", "A1 MOVS, shift or rotate by value", "T3 MOV, shift or rotate by value", and "T3 MOVS, shift or rotate by value" variants: is the type of shift to be applied to the source register,
stype
<shift>
00
LSL
01
LSR
10
ASR
11
ROR
<shift>
For the "T2" variant: is the type of shift to be applied to the source register,
op
<shift>
00
LSL
01
LSR
10
ASR
<amount>
For the "A1 MOV, shift or rotate by value" and "A1 MOVS, shift or rotate by value" variants: is the shift amount, in the range 0 to 31 (when <shift> = LSL), or 1 to 31 (when <shift> = ROR) or 1 to 32 (when <shift> = LSR or ASR), encoded in the "imm5" field as <amount> modulo 32.
<amount>
For the "T2" variant: is the shift amount, in the range 1 to 31 (when <shift> = LSL or ROR) or 1 to 32 (when <shift> = LSR or ASR), encoded in the "imm5" field as <amount> modulo 32.
<amount>
For the "T3 MOV, shift or rotate by value" and "T3 MOVS, shift or rotate by value" variants: is the shift amount, in the range 0 to 31 (when <shift> = LSL) or 1 to 31 (when <shift> = ROR), or 1 to 32 (when <shift> = LSR or ASR), encoded in the "imm3:imm2" field as <amount> modulo 32.
Alias Conditions
if ConditionPassed() then
EncodingSpecificOperations();
let (shifted, carry) : (bits(32), bit) = Shift_C{32}(R(m), shift_t, shift_n, PSTATE.C);
let result : bits(32) = shifted;
if d == 15 then
if setflags then
ALUExceptionReturn(result);
else
ALUWritePC(result);
end;
else
R(d) = result;
if setflags then
PSTATE.N = result[31];
PSTATE.Z = IsZeroBit{32}(result);
PSTATE.C = carry;
// PSTATE.V unchanged
end;
end;
end;
2026-03-26 20:27:25
2026-03_rel