PLD, PLDW (immediate)
Preload Data (immediate)
Preload Data (immediate) signals the memory system that data memory
accesses from a specified address are likely in the near future. The
memory system can respond by taking actions that are expected to
speed up the memory accesses when they do occur, such as preloading
the cache line containing the specified address into the data cache.
The PLD instruction signals that the likely memory access is a
read, and the PLDW instruction signals that it is a write.
The effect of a PLD or PLDW instruction is
IMPLEMENTATION DEFINED. For more information,
see Preloading caches.
For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
and
T2
)
.
1
1
1
1
0
1
0
1
0
1
!= 1111
(1)
(1)
(1)
(1)
1
PLD{<c>}{<q>} [<Rn> {, #{+/-}<imm>}]
0
PLDW{<c>}{<q>} [<Rn> {, #{+/-}<imm>}]
if Rn == '1111' then See("PLD (literal)"); end;
let n : integer = UInt(Rn);
let imm32 : bits(32) = ZeroExtend{}(imm12);
let add : boolean = (U == '1');
let is_pldw : boolean = (R == '0');
1
1
1
1
1
0
0
0
1
0
1
!= 1111
1
1
1
1
0
PLD{<c>}{<q>} [<Rn> {, #{+}<imm>}]
1
PLDW{<c>}{<q>} [<Rn> {, #{+}<imm>}]
if Rn == '1111' then See("PLD (literal)"); end;
let n : integer = UInt(Rn);
let imm32 : bits(32) = ZeroExtend{}(imm12);
let add : boolean = TRUE;
let is_pldw : boolean = (W == '1');
1
1
1
1
1
0
0
0
0
0
1
!= 1111
1
1
1
1
1
1
0
0
0
PLD{<c>}{<q>} [<Rn> {, #-<imm>}]
1
PLDW{<c>}{<q>} [<Rn> {, #-<imm>}]
if Rn == '1111' then See("PLD (literal)"); end;
let n : integer = UInt(Rn);
let imm32 : bits(32) = ZeroExtend{}(imm8);
let add : boolean = FALSE;
let is_pldw : boolean = (W == '1');
<c>
For the "A1 Preload read" and "A1 Preload write" variants: see Standard assembler syntax fields. Must be AL or omitted.
<c>
For the "T1 Preload read", "T1 Preload write", "T2 Preload read", and "T2 Preload write" variants: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Rn>
Is the general-purpose base register, encoded in the "Rn" field. If the PC is used, see PLD (literal).
+/-
Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
<imm>
For the "A1 Preload read" and "A1 Preload write" variants: is the optional 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.
<imm>
For the "T1 Preload read" and "T1 Preload write" variants: is an optional 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.
<imm>
For the "T2 Preload read" and "T2 Preload write" variants: is an 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm8" field.
+
Specifies the offset is added to the base register.
if ConditionPassed() then
EncodingSpecificOperations();
let address : bits(32) = if add then (R(n) + imm32) else (R(n) - imm32);
if is_pldw then
Hint_PreloadDataForWrite(address);
else
Hint_PreloadData(address);
end;
end;
2026-03-26 20:27:25
2026-03_rel