PLD, PLDW (register)
Preload Data (register)
Preload Data (register) signals the memory system that data memory
accesses from a specified address are likely in the near future. The
memory system can respond by taking actions that are expected to
speed up the memory accesses when they do occur, such as preloading
the cache line containing the specified address into the data cache.
The PLD instruction signals that the likely memory access is a
read, and the PLDW instruction signals that it is a write.
The effect of a PLD or PLDW instruction is
IMPLEMENTATION DEFINED. For more information,
see Preloading caches.
For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
1
1
1
1
0
1
1
1
0
1
(1)
(1)
(1)
(1)
0
1
PLD{<c>}{<q>} [<Rn>, {+/-}<Rm> {, <shift> #<amount>}]
1
0
0
0
0
0
1
1
PLD{<c>}{<q>} [<Rn>, {+/-}<Rm> , RRX]
0
PLDW{<c>}{<q>} [<Rn>, {+/-}<Rm> {, <shift> #<amount>}]
0
0
0
0
0
0
1
1
PLDW{<c>}{<q>} [<Rn>, {+/-}<Rm> , RRX]
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let add : boolean = (U == '1');
let is_pldw : boolean = (R == '0');
let (shift_t, shift_n) : (SRType, integer) = DecodeImmShift(stype, imm5);
if m == 15 || (n == 15 && is_pldw) then UnpredictableProcedure(); end;
1
1
1
1
1
0
0
0
0
0
1
!= 1111
1
1
1
1
0
0
0
0
0
0
0
PLD{<c>}{<q>} [<Rn>, {+}<Rm> {, LSL #<amount>}]
1
PLDW{<c>}{<q>} [<Rn>, {+}<Rm> {, LSL #<amount>}]
if Rn == '1111' then See("PLD (literal)"); end;
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let add : boolean = TRUE;
let is_pldw : boolean = (W == '1');
let shift_t : SRType = SRType_LSL;
let shift_n : integer = UInt(imm2);
// Armv8-A removes UNPREDICTABLE for R13
if m == 15 then UnpredictableProcedure(); end;
<c>
For the "Preload read, optional shift or rotate", "Preload read, rotate right with extend", "Preload write, optional shift or rotate", and "Preload write, rotate right with extend" variants: see Standard assembler syntax fields. <c> must be AL or omitted.
<c>
For the "Preload read" and "Preload write" variants: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Rn>
For the "Preload read, optional shift or rotate", "Preload read, rotate right with extend", "Preload write, optional shift or rotate", and "Preload write, rotate right with extend" variants: is the general-purpose base register, encoded in the "Rn" field. The PC can be used.
<Rn>
For the "Preload read" and "Preload write" variants: is the general-purpose base register, encoded in the "Rn" field.
+/-
Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and
<Rm>
Is the general-purpose index register, encoded in the "Rm" field.
<shift>
Is the type of shift to be applied to the index register,
stype
<shift>
00
LSL
01
LSR
10
ASR
11
ROR
<amount>
For the "Preload read, optional shift or rotate" and "Preload write, optional shift or rotate" variants: is the shift amount, in the range 1 to 31 (when <shift> = LSL or ROR) or 1 to 32 (when <shift> = LSR or ASR) encoded in the "imm5" field as <amount> modulo 32.
<amount>
For the "Preload read" and "Preload write" variants: is the shift amount, in the range 0 to 3, defaulting to 0 and encoded in the "imm2" field.
+
Specifies the index register is added to the base register.
if ConditionPassed() then
EncodingSpecificOperations();
let offset : bits(32) = Shift{}(R(m), shift_t, shift_n, PSTATE.C);
let address : bits(32) = if add then (R(n) + offset) else (R(n) - offset);
if is_pldw then
Hint_PreloadDataForWrite(address);
else
Hint_PreloadData(address);
end;
end;
2026-03-26 20:27:25
2026-03_rel