RSC, RSCS (register)
Reverse Subtract with Carry (register)
Reverse Subtract with Carry (register) subtracts a register
value and the value of NOT (Carry flag) from an optionally-shifted
register value, and writes the result to the destination register.
If the destination register is not the PC, the RSCS variant of the
instruction updates the condition flags based on the result.
The field descriptions for <Rd> identify the encodings
where the PC is permitted as the destination register. ARM
deprecates any use of these encodings. However, when the destination
register is the PC:
The RSC variant of the instruction is an interworking branch, see Pseudocode description of operations on the AArch32 general-purpose registers and the PC.
The RSCS variant of the instruction performs an exception return without the use of the stack. In this case:
The PE branches to the address written to the PC, and restores PSTATE from SPSR_<current_mode>.
The PE checks SPSR_<current_mode> for an illegal return event. See Illegal return events from AArch32 state.
The instruction is UNDEFINED in Hyp mode.
The instruction is CONSTRAINED UNPREDICTABLE in User mode and System mode.
This instruction is a data-independent-time instruction as described in About the DIT bit.
!= 1111
0
0
0
0
1
1
1
0
0
0
0
0
0
0
1
1
RSC{<c>}{<q>} {<Rd>, }<Rn>, <Rm>, RRX
0
RSC{<c>}{<q>} {<Rd>, }<Rn>, <Rm> {, <shift> #<amount>}
1
0
0
0
0
0
1
1
RSCS{<c>}{<q>} {<Rd>, }<Rn>, <Rm>, RRX
1
RSCS{<c>}{<q>} {<Rd>, }<Rn>, <Rm> {, <shift> #<amount>}
let d : integer = UInt(Rd);
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let setflags : boolean = (S == '1');
let (shift_t, shift_n) : (SRType, integer) = DecodeImmShift(stype, imm5);
<c>
See Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Rd>
Is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <Rn>. Arm deprecates using the PC as the destination register, but if the PC is used:
For the RSC variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see Pseudocode description of operations on the AArch32 general-purpose registers and the PC.
For the RSCS variant, the instruction performs an exception return, that restores PSTATE from SPSR_<current_mode>.
<Rn>
Is the first general-purpose source register, encoded in the "Rn" field. The PC can be used, but this is deprecated.
<Rm>
Is the second general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated.
<shift>
Is the type of shift to be applied to the second source register,
stype
<shift>
00
LSL
01
LSR
10
ASR
11
ROR
<amount>
Is the shift amount, in the range 1 to 31 (when <shift> = LSL or ROR) or 1 to 32 (when <shift> = LSR or ASR) encoded in the "imm5" field as <amount> modulo 32.
if ConditionPassed() then
EncodingSpecificOperations();
let shifted : bits(32) = Shift{}(R(m), shift_t, shift_n, PSTATE.C);
let (result, nzcv) : (bits(32), bits(4)) = AddWithCarry{32}(NOT(R(n)), shifted, PSTATE.C);
if d == 15 then
if setflags then
ALUExceptionReturn(result);
else
ALUWritePC(result);
end;
else
R(d) = result;
if setflags then
PSTATE.[N,Z,C,V] = nzcv;
end;
end;
end;
2026-03-26 20:27:25
2026-03_rel