SHA256SU0
SHA256 schedule update 0
SHA256 schedule update 0.
For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
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1
0
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1
0
0
0
1
1
1
1
0
SHA256SU0.32 <Qd>, <Qm>
if !IsFeatureImplemented(FEAT_SHA256) then Undefined(); end;
if size != '10' then Undefined(); end;
if Vd[0] == '1' || Vm[0] == '1' then Undefined(); end;
let d : integer = UInt(D::Vd);
let m : integer = UInt(M::Vm);
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0
SHA256SU0.32 <Qd>, <Qm>
if InITBlock() then UnpredictableProcedure(); end;
if !IsFeatureImplemented(FEAT_SHA256) then Undefined(); end;
if size != '10' then Undefined(); end;
if Vd[0] == '1' || Vm[0] == '1' then Undefined(); end;
let d : integer = UInt(D::Vd);
let m : integer = UInt(M::Vm);
<Qd>
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.
<Qm>
Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.
if ConditionPassed() then
var result : bits(128);
EncodingSpecificOperations();
CheckCryptoEnabled32();
let x : bits(128) = Q(d>>1);
let y : bits(128) = Q(m>>1);
let t : bits(128) = y[31:0] :: x[127:32];
for e = 0 to 3 do
var elt : bits(32) = t[e*:32];
elt = ROR(elt, 7) XOR ROR(elt, 18) XOR LSR(elt, 3);
result[e*:32] = elt + x[e*:32];
end;
Q(d>>1) = result;
end;
2026-03-26 20:27:25
2026-03_rel