<?xml version="1.0" ?><?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?><!DOCTYPE instructionsection  PUBLIC '-//ARM//DTD instructionsection //EN'  'iform-p.dtd'><!-- Copyright (c) 2010-2026 Arm Limited or its affiliates. All rights reserved. --><!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. --><instructionsection id="SMLAD" title="SMLAD, SMLADX -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general"/>
  </docvars>
  <heading>SMLAD, SMLADX</heading>
  <desc>
    <brief>
      <para>Signed Multiply Accumulate Dual</para>
    </brief>
    <authored>
      <para>Signed Multiply Accumulate Dual performs two signed 16 x 16-bit
multiplications. It adds the products to a 32-bit accumulate operand.</para>
      <para>Optionally, the instruction can exchange the halfwords of
the second operand before performing the arithmetic. This produces
top x bottom and bottom x top multiplication.</para>
      <para>This instruction sets <xref linkend="ARMARM_CHDEDFDC">PSTATE</xref>.Q to 1 if the accumulate operation
overflows. Overflow cannot occur during the multiplications.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>CONSTRAINED UNPREDICTABLE</arm-defined-word> behavior of this instruction, see <xref linkend="ARMARM_CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"/>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1"/>
        <docvar key="instr-class" value="general"/>
        <docvar key="isa" value="A32"/>
      </docvars>
      <iclassintro count="2"/>
      <regdiagram form="32" psname="A32.media.smul_div.SMLAD_A1" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" usename="1" settings="3" psbits="xxx">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rd" usename="1">
          <c colspan="4"/>
        </box>
        <box hibit="15" width="4" name="Ra" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="11" width="4" name="Rm" usename="1">
          <c colspan="4"/>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="1" name="M" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="4" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rn" usename="1">
          <c colspan="4"/>
        </box>
      </regdiagram>
      <encoding name="SMLAD_A1" oneofinclass="2" oneof="4" label="SMLAD" bitdiffs="M == 0">
        <docvars>
          <docvar key="armarmheading" value="A1"/>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A32"/>
          <docvar key="mnemonic" value="SMLAD"/>
        </docvars>
        <box hibit="5" width="1" name="M">
          <c>0</c>
        </box>
        <asmtemplate><text>SMLAD{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="c__5">&lt;c&gt;</a><text>}{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="qw_option">&lt;q&gt;</a><text>}  </text><a hover="Is the general-purpose destination register, encoded in the &quot;Rd&quot; field." link="Rd">&lt;Rd&gt;</a><text>, </text><a hover="Is the first general-purpose source register, encoded in the &quot;Rn&quot; field." link="Rn">&lt;Rn&gt;</a><text>, </text><a hover="Is the second general-purpose source register, encoded in the &quot;Rm&quot; field." link="Rm">&lt;Rm&gt;</a><text>, </text><a hover="Is the third general-purpose source register holding the addend, encoded in the &quot;Ra&quot; field." link="Ra">&lt;Ra&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMLADX_A1" oneofinclass="2" oneof="4" label="SMLADX" bitdiffs="M == 1">
        <docvars>
          <docvar key="armarmheading" value="A1"/>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A32"/>
          <docvar key="mnemonic" value="SMLADX"/>
        </docvars>
        <box hibit="5" width="1" name="M">
          <c>1</c>
        </box>
        <asmtemplate><text>SMLADX{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="c__5">&lt;c&gt;</a><text>}{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="qw_option">&lt;q&gt;</a><text>}  </text><a hover="Is the general-purpose destination register, encoded in the &quot;Rd&quot; field." link="Rd">&lt;Rd&gt;</a><text>, </text><a hover="Is the first general-purpose source register, encoded in the &quot;Rn&quot; field." link="Rn">&lt;Rn&gt;</a><text>, </text><a hover="Is the second general-purpose source register, encoded in the &quot;Rm&quot; field." link="Rm">&lt;Rm&gt;</a><text>, </text><a hover="Is the third general-purpose source register holding the addend, encoded in the &quot;Ra&quot; field." link="Ra">&lt;Ra&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="A32.media.smul_div.SMLAD_A1" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if Ra == '1111' then See(&quot;SMUAD&quot;); end;
let d : integer = UInt(Rd);
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let a : integer = UInt(Ra);
let m_swap : boolean = (M == '1');
if d == 15 || n == 15 || m == 15 then UnpredictableProcedure(); end;</pstext></ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1"/>
        <docvar key="instr-class" value="general"/>
        <docvar key="isa" value="T32"/>
      </docvars>
      <iclassintro count="2"/>
      <regdiagram form="16x2" psname="T32.w.mul.mul_abd.SMLAD_T1" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" usename="1" settings="3" psbits="xxx">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"/>
        </box>
        <box hibit="15" width="4" name="Ra" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"/>
        </box>
        <box hibit="7" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="4" width="1" name="M" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"/>
        </box>
      </regdiagram>
      <encoding name="SMLAD_T1" oneofinclass="2" oneof="4" label="SMLAD" bitdiffs="M == 0">
        <docvars>
          <docvar key="armarmheading" value="T1"/>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="T32"/>
          <docvar key="mnemonic" value="SMLAD"/>
        </docvars>
        <box hibit="4" width="1" name="M">
          <c>0</c>
        </box>
        <asmtemplate><text>SMLAD{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="c__5">&lt;c&gt;</a><text>}{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="qw_option">&lt;q&gt;</a><text>}  </text><a hover="Is the general-purpose destination register, encoded in the &quot;Rd&quot; field." link="Rd">&lt;Rd&gt;</a><text>, </text><a hover="Is the first general-purpose source register, encoded in the &quot;Rn&quot; field." link="Rn">&lt;Rn&gt;</a><text>, </text><a hover="Is the second general-purpose source register, encoded in the &quot;Rm&quot; field." link="Rm">&lt;Rm&gt;</a><text>, </text><a hover="Is the third general-purpose source register holding the addend, encoded in the &quot;Ra&quot; field." link="Ra">&lt;Ra&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMLADX_T1" oneofinclass="2" oneof="4" label="SMLADX" bitdiffs="M == 1">
        <docvars>
          <docvar key="armarmheading" value="T1"/>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="T32"/>
          <docvar key="mnemonic" value="SMLADX"/>
        </docvars>
        <box hibit="4" width="1" name="M">
          <c>1</c>
        </box>
        <asmtemplate><text>SMLADX{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="c__5">&lt;c&gt;</a><text>}{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="qw_option">&lt;q&gt;</a><text>}  </text><a hover="Is the general-purpose destination register, encoded in the &quot;Rd&quot; field." link="Rd">&lt;Rd&gt;</a><text>, </text><a hover="Is the first general-purpose source register, encoded in the &quot;Rn&quot; field." link="Rn">&lt;Rn&gt;</a><text>, </text><a hover="Is the second general-purpose source register, encoded in the &quot;Rm&quot; field." link="Rm">&lt;Rm&gt;</a><text>, </text><a hover="Is the third general-purpose source register holding the addend, encoded in the &quot;Ra&quot; field." link="Ra">&lt;Ra&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="T32.w.mul.mul_abd.SMLAD_T1" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if Ra == '1111' then See(&quot;SMUAD&quot;); end;
let d : integer = UInt(Rd);
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let a : integer = UInt(Ra);
let m_swap : boolean = (M == '1');
// Armv8-A removes UNPREDICTABLE for R13
if d == 15 || n == 15 || m == 15 then UnpredictableProcedure(); end;</pstext></ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SMLAD_A1, SMLADX_A1, SMLAD_T1, SMLADX_T1" symboldefcount="1">
      <symbol link="c__5">&lt;c&gt;</symbol>
      <account encodedin="cond">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLAD_A1, SMLADX_A1, SMLAD_T1, SMLADX_T1" symboldefcount="1">
      <symbol link="qw_option">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLAD_A1, SMLADX_A1, SMLAD_T1, SMLADX_T1" symboldefcount="1">
      <symbol link="Rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the &quot;Rd&quot; field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLAD_A1, SMLADX_A1, SMLAD_T1, SMLADX_T1" symboldefcount="1">
      <symbol link="Rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the &quot;Rn&quot; field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLAD_A1, SMLADX_A1, SMLAD_T1, SMLADX_T1" symboldefcount="1">
      <symbol link="Rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the &quot;Rm&quot; field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLAD_A1, SMLADX_A1, SMLAD_T1, SMLADX_T1" symboldefcount="1">
      <symbol link="Ra">&lt;Ra&gt;</symbol>
      <account encodedin="Ra">
        <intro>
          <para>Is the third general-purpose source register holding the addend, encoded in the &quot;Ra&quot; field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="A32.media.smul_div.SMLAD_A1" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="func_ConditionPassed_0" file="shared_pseudocode.xml">ConditionPassed</a>() then
    EncodingSpecificOperations();
    let operand2 : bits(32) = if m_swap then ROR(<a link="accessor_R_1" file="shared_pseudocode.xml">R</a>(m),16) else <a link="accessor_R_1" file="shared_pseudocode.xml">R</a>(m);
    let product1 : integer = SInt(<a link="accessor_R_1" file="shared_pseudocode.xml">R</a>(n)[15:0]) * SInt(operand2[15:0]);
    let product2 : integer = SInt(<a link="accessor_R_1" file="shared_pseudocode.xml">R</a>(n)[31:16]) * SInt(operand2[31:16]);
    let result : integer = product1 + product2 + SInt(<a link="accessor_R_1" file="shared_pseudocode.xml">R</a>(a));
    <a link="accessor_R_1" file="shared_pseudocode.xml">R</a>(d) = result[31:0];
    if result != SInt(result[31:0]) then  // Signed overflow
        <a link="global_PSTATE" file="shared_pseudocode.xml">PSTATE</a>.Q = '1';
    end;
end;</pstext></ps>
  </ps_section>
  <timestamp>2026-03-26 20:27:25</timestamp>
  <commit_id>2026-03_rel</commit_id>
</instructionsection>