<?xml version="1.0" ?><?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?><!DOCTYPE instructionsection  PUBLIC '-//ARM//DTD instructionsection //EN'  'iform-p.dtd'><!-- Copyright (c) 2010-2026 Arm Limited or its affiliates. All rights reserved. --><!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. --><instructionsection id="SMLAL" title="SMLAL, SMLALS -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general"/>
  </docvars>
  <heading>SMLAL, SMLALS</heading>
  <desc>
    <brief>
      <para>Signed Multiply Accumulate Long</para>
    </brief>
    <authored>
      <para>Signed Multiply Accumulate Long multiplies two signed 32-bit values
to produce a 64-bit value, and accumulates this with a 64-bit value.</para>
      <para>In A32 instructions, the condition flags can optionally be updated
based on the result. Use of this option adversely affects
performance on many implementations.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>CONSTRAINED UNPREDICTABLE</arm-defined-word> behavior of this instruction, see <xref linkend="ARMARM_CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <operationalnote>
      <operationalnote_content>
        <para>This instruction is a data-independent-time instruction as described in <xref linkend="ARMARM_BEIIDCEG">About the DIT bit</xref>.</para>
      </operationalnote_content>
    </operationalnote>
  </operationalnotes>
  <alias_list howmany="0"/>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1"/>
        <docvar key="instr-class" value="general"/>
        <docvar key="isa" value="A32"/>
      </docvars>
      <iclassintro count="2"/>
      <regdiagram form="32" psname="A32.dp.mul_word.SMLALS_A1" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" usename="1" settings="3" psbits="xxx">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" width="1" name="S" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="19" width="4" name="RdHi" usename="1">
          <c colspan="4"/>
        </box>
        <box hibit="15" width="4" name="RdLo" usename="1">
          <c colspan="4"/>
        </box>
        <box hibit="11" width="4" name="Rm" usename="1">
          <c colspan="4"/>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rn" usename="1">
          <c colspan="4"/>
        </box>
      </regdiagram>
      <encoding name="SMLALS_A1" oneofinclass="2" oneof="3" label="Flag setting" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="A1"/>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A32"/>
          <docvar key="cond-setting" value="s"/>
          <docvar key="mnemonic" value="SMLALS"/>
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate><text>SMLALS{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="c__5">&lt;c&gt;</a><text>}{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="qw_option">&lt;q&gt;</a><text>}  </text><a hover="Is the general-purpose source register holding the lower 32 bits of the addend, and the destination register for the lower 32 bits of the result, encoded in the &quot;RdLo&quot; field." link="RdLo">&lt;RdLo&gt;</a><text>, </text><a hover="Is the general-purpose source register holding the upper 32 bits of the addend, and the destination register for the upper 32 bits of the result, encoded in the &quot;RdHi&quot; field." link="RdHi">&lt;RdHi&gt;</a><text>, </text><a hover="Is the first general-purpose source register holding the multiplicand, encoded in the &quot;Rn&quot; field." link="Rn__10">&lt;Rn&gt;</a><text>, </text><a hover="Is the second general-purpose source register holding the multiplier, encoded in the &quot;Rm&quot; field." link="Rm__15">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMLAL_A1" oneofinclass="2" oneof="3" label="Not flag setting" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="A1"/>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A32"/>
          <docvar key="cond-setting" value="no-s"/>
          <docvar key="mnemonic" value="SMLAL"/>
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>SMLAL{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="c__5">&lt;c&gt;</a><text>}{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="qw_option">&lt;q&gt;</a><text>}  </text><a hover="Is the general-purpose source register holding the lower 32 bits of the addend, and the destination register for the lower 32 bits of the result, encoded in the &quot;RdLo&quot; field." link="RdLo">&lt;RdLo&gt;</a><text>, </text><a hover="Is the general-purpose source register holding the upper 32 bits of the addend, and the destination register for the upper 32 bits of the result, encoded in the &quot;RdHi&quot; field." link="RdHi">&lt;RdHi&gt;</a><text>, </text><a hover="Is the first general-purpose source register holding the multiplicand, encoded in the &quot;Rn&quot; field." link="Rn__10">&lt;Rn&gt;</a><text>, </text><a hover="Is the second general-purpose source register holding the multiplier, encoded in the &quot;Rm&quot; field." link="Rm__15">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="A32.dp.mul_word.SMLALS_A1" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">let dLo : integer = UInt(RdLo);
let dHi : integer = UInt(RdHi);
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let setflags : boolean = (S == '1');
if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UnpredictableProcedure(); end;
if dHi == dLo then UnpredictableProcedure(); end;</pstext></ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">dHi == dLo</pstext></cu_cause>
          <cu_type constraint="Constraint_UNDEF"/>
          <cu_type constraint="Constraint_NOP"/>
          <cu_type constraint="Constraint_UNKNOWN"/>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1"/>
        <docvar key="instr-class" value="general"/>
        <docvar key="isa" value="T32"/>
        <docvar key="mnemonic" value="SMLAL"/>
      </docvars>
      <iclassintro count="1"/>
      <regdiagram form="16x2" psname="T32.w.lmul_div.lmul.SMLAL_T1" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" usename="1" settings="3" psbits="xxx">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"/>
        </box>
        <box hibit="15" width="4" name="RdLo" usename="1">
          <c colspan="4"/>
        </box>
        <box hibit="11" width="4" name="RdHi" usename="1">
          <c colspan="4"/>
        </box>
        <box hibit="7" width="4" name="op2" usename="1" settings="4" psbits="xxxx">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"/>
        </box>
      </regdiagram>
      <encoding name="SMLAL_T1" oneofinclass="1" oneof="3" label="">
        <docvars>
          <docvar key="armarmheading" value="T1"/>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="T32"/>
          <docvar key="mnemonic" value="SMLAL"/>
        </docvars>
        <asmtemplate><text>SMLAL{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="c__5">&lt;c&gt;</a><text>}{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="qw_option">&lt;q&gt;</a><text>}  </text><a hover="Is the general-purpose source register holding the lower 32 bits of the addend, and the destination register for the lower 32 bits of the result, encoded in the &quot;RdLo&quot; field." link="RdLo">&lt;RdLo&gt;</a><text>, </text><a hover="Is the general-purpose source register holding the upper 32 bits of the addend, and the destination register for the upper 32 bits of the result, encoded in the &quot;RdHi&quot; field." link="RdHi">&lt;RdHi&gt;</a><text>, </text><a hover="Is the first general-purpose source register holding the multiplicand, encoded in the &quot;Rn&quot; field." link="Rn__10">&lt;Rn&gt;</a><text>, </text><a hover="Is the second general-purpose source register holding the multiplier, encoded in the &quot;Rm&quot; field." link="Rm__15">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="T32.w.lmul_div.lmul.SMLAL_T1" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">let dLo : integer = UInt(RdLo);
let dHi : integer = UInt(RdHi);
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let setflags : boolean = FALSE;
if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UnpredictableProcedure(); end;
// Armv8-A removes UNPREDICTABLE for R13
if dHi == dLo then UnpredictableProcedure(); end;</pstext></ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">dHi == dLo</pstext></cu_cause>
          <cu_type constraint="Constraint_UNDEF"/>
          <cu_type constraint="Constraint_NOP"/>
          <cu_type constraint="Constraint_UNKNOWN"/>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SMLALS_A1, SMLAL_A1, SMLAL_T1" symboldefcount="1">
      <symbol link="c__5">&lt;c&gt;</symbol>
      <account encodedin="cond">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLALS_A1, SMLAL_A1, SMLAL_T1" symboldefcount="1">
      <symbol link="qw_option">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLALS_A1, SMLAL_A1, SMLAL_T1" symboldefcount="1">
      <symbol link="RdLo">&lt;RdLo&gt;</symbol>
      <account encodedin="RdLo">
        <intro>
          <para>Is the general-purpose source register holding the lower 32 bits of the addend, and the destination register for the lower 32 bits of the result, encoded in the &quot;RdLo&quot; field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLALS_A1, SMLAL_A1, SMLAL_T1" symboldefcount="1">
      <symbol link="RdHi">&lt;RdHi&gt;</symbol>
      <account encodedin="RdHi">
        <intro>
          <para>Is the general-purpose source register holding the upper 32 bits of the addend, and the destination register for the upper 32 bits of the result, encoded in the &quot;RdHi&quot; field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLALS_A1, SMLAL_A1, SMLAL_T1" symboldefcount="1">
      <symbol link="Rn__10">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register holding the multiplicand, encoded in the &quot;Rn&quot; field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLALS_A1, SMLAL_A1, SMLAL_T1" symboldefcount="1">
      <symbol link="Rm__15">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register holding the multiplier, encoded in the &quot;Rm&quot; field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="A32.dp.mul_word.SMLALS_A1" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="func_ConditionPassed_0" file="shared_pseudocode.xml">ConditionPassed</a>() then
    EncodingSpecificOperations();
    let result : integer = SInt(<a link="accessor_R_1" file="shared_pseudocode.xml">R</a>(n)) * SInt(<a link="accessor_R_1" file="shared_pseudocode.xml">R</a>(m)) + SInt(<a link="accessor_R_1" file="shared_pseudocode.xml">R</a>(dHi)::<a link="accessor_R_1" file="shared_pseudocode.xml">R</a>(dLo));
    <a link="accessor_R_1" file="shared_pseudocode.xml">R</a>(dHi) = result[63:32];
    <a link="accessor_R_1" file="shared_pseudocode.xml">R</a>(dLo) = result[31:0];
    if setflags then
        <a link="global_PSTATE" file="shared_pseudocode.xml">PSTATE</a>.N = result[63];
        <a link="global_PSTATE" file="shared_pseudocode.xml">PSTATE</a>.Z = <a link="func_IsZeroBit_2" file="shared_pseudocode.xml">IsZeroBit</a>{64}(result[63:0]);
        // PSTATE.C, PSTATE.V unchanged
    end;
end;</pstext></ps>
  </ps_section>
  <timestamp>2026-03-26 20:27:25</timestamp>
  <commit_id>2026-03_rel</commit_id>
</instructionsection>