SMLALBB, SMLALBT, SMLALTB, SMLALTT
Signed Multiply Accumulate Long (halfwords)
Signed
Multiply Accumulate Long (halfwords) multiplies two signed 16-bit
values to produce a 32-bit value, and accumulates this with a 64-bit
value. The multiply acts on two signed 16-bit quantities, taken
from either the bottom or the top half of their respective source
registers. The other halves of these source registers are ignored.
The 32-bit product is sign-extended and accumulated with a 64-bit
accumulate value.
Overflow is possible during this instruction, but only as
a result of the 64-bit addition. This overflow is not detected if
it occurs. Instead, the result wraps around modulo 264.
For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
!= 1111
0
0
0
1
0
1
0
0
1
0
0
0
SMLALBB{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>
1
0
SMLALBT{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>
0
1
SMLALTB{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>
1
1
SMLALTT{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>
let dLo : integer = UInt(RdLo);
let dHi : integer = UInt(RdHi);
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let n_index : integer = UInt(N);
let m_index : integer = UInt(M);
if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UnpredictableProcedure(); end;
if dHi == dLo then UnpredictableProcedure(); end;
dHi == dLo
1
1
1
1
1
0
1
1
1
1
0
0
1
0
0
0
SMLALBB{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>
0
1
SMLALBT{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>
1
0
SMLALTB{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>
1
1
SMLALTT{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>
let dLo : integer = UInt(RdLo);
let dHi : integer = UInt(RdHi);
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let n_index : integer = UInt(N);
let m_index : integer = UInt(M);
if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UnpredictableProcedure(); end;
// Armv8-A removes UNPREDICTABLE for R13
if dHi == dLo then UnpredictableProcedure(); end;
dHi == dLo
<c>
See Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<RdLo>
Is the general-purpose source register holding the lower 32 bits of the addend, and the destination register for the lower 32 bits of the result, encoded in the "RdLo" field.
<RdHi>
Is the general-purpose source register holding the upper 32 bits of the addend, and the destination register for the upper 32 bits of the result, encoded in the "RdHi" field.
<Rn>
For the "A1 SMLALBB", "A1 SMLALBT", "A1 SMLALTB", and "A1 SMLALTT" variants: is the first general-purpose source register holding the multiplicand in the bottom or top half (selected by <x>), encoded in the "Rn" field.
<Rn>
For the "T1 SMLALBB", "T1 SMLALBT", "T1 SMLALTB", and "T1 SMLALTT" variants: is the first general-purpose source register holding the multiplicand in the bottom or top half (selected by <x>), encoded in the "Rn" field.
<Rm>
For the "A1 SMLALBB", "A1 SMLALBT", "A1 SMLALTB", and "A1 SMLALTT" variants: is the second general-purpose source register holding the multiplier in the bottom or top half (selected by <y>), encoded in the "Rm" field.
<Rm>
For the "T1 SMLALBB", "T1 SMLALBT", "T1 SMLALTB", and "T1 SMLALTT" variants: is the second general-purpose source register holding the multiplier in the bottom or top half (selected by <x>), encoded in the "Rm" field.
if ConditionPassed() then
EncodingSpecificOperations();
let operand1 : bits(16) = R(n)[n_index*:16];
let operand2 : bits(16) = R(m)[m_index*:16];
let result : integer = SInt(operand1) * SInt(operand2) + SInt(R(dHi)::R(dLo));
R(dHi) = result[63:32];
R(dLo) = result[31:0];
end;
2026-03-26 20:27:25
2026-03_rel