SMLALD, SMLALDX
Signed Multiply Accumulate Long Dual
Signed
Multiply Accumulate Long Dual performs two signed 16 x 16-bit multiplications.
It adds the products to a 64-bit accumulate operand.
Optionally, the instruction can exchange the halfwords of
the second operand before performing the arithmetic. This produces
top x bottom and bottom x top multiplication.
Overflow is possible during this instruction, but only as
a result of the 64-bit addition. This overflow is not detected if
it occurs. Instead, the result wraps around modulo 264.
For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
!= 1111
0
1
1
1
0
1
0
0
0
0
1
0
SMLALD{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>
1
SMLALDX{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>
let dLo : integer = UInt(RdLo);
let dHi : integer = UInt(RdHi);
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let m_swap : boolean = (M == '1');
if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UnpredictableProcedure(); end;
if dHi == dLo then UnpredictableProcedure(); end;
dHi == dLo
1
1
1
1
1
0
1
1
1
1
0
0
1
1
0
0
SMLALD{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>
1
SMLALDX{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>
let dLo : integer = UInt(RdLo);
let dHi : integer = UInt(RdHi);
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let m_swap : boolean = (M == '1');
if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UnpredictableProcedure(); end;
// Armv8-A removes UNPREDICTABLE for R13
if dHi == dLo then UnpredictableProcedure(); end;
dHi == dLo
<c>
See Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<RdLo>
Is the general-purpose source register holding the lower 32 bits of the addend, and the destination register for the lower 32 bits of the result, encoded in the "RdLo" field.
<RdHi>
Is the general-purpose source register holding the upper 32 bits of the addend, and the destination register for the upper 32 bits of the result, encoded in the "RdHi" field.
<Rn>
Is the first general-purpose source register, encoded in the "Rn" field.
<Rm>
Is the second general-purpose source register, encoded in the "Rm" field.
if ConditionPassed() then
EncodingSpecificOperations();
let operand2 : bits(32) = if m_swap then ROR(R(m),16) else R(m);
let product1 : integer = SInt(R(n)[15:0]) * SInt(operand2[15:0]);
let product2 : integer = SInt(R(n)[31:16]) * SInt(operand2[31:16]);
let result : integer = product1 + product2 + SInt(R(dHi)::R(dLo));
R(dHi) = result[63:32];
R(dLo) = result[31:0];
end;
2026-03-26 20:27:25
2026-03_rel