STRB (register)
Store Register Byte (register)
Store Register Byte (register) calculates an address from a base
register value and an offset register value, and stores a byte from
a register to memory. The offset register value can optionally be
shifted. For information about memory accesses see
Memory accesses.
For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
and
T2
)
.
!= 1111
0
1
1
1
0
0
1
0
STRB{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}]
0
0
STRB{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>}
1
1
STRB{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}]!
if P == '0' && W == '1' then See("STRBT"); end;
let t : integer = UInt(Rt);
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let index : boolean = (P == '1');
let add : boolean = (U == '1');
let wback : boolean = (P == '0') || (W == '1');
let (shift_t, shift_n) : (SRType, integer) = DecodeImmShift(stype, imm5);
if t == 15 || m == 15 then UnpredictableProcedure(); end;
if wback && (n == 15 || n == t) then UnpredictableProcedure(); end;
t == 15
The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is UNKNOWN.
wback && n == t
wback && n == 15
The instruction uses the addressing mode described in the equivalent immediate offset instruction.
0
1
0
1
0
1
0
STRB{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>]
let t : integer = UInt(Rt);
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let index : boolean = TRUE;
let add : boolean = TRUE;
let wback : boolean = FALSE;
let shift_t : SRType = SRType_LSL;
let shift_n : integer = 0;
1
1
1
1
1
0
0
0
0
0
0
0
!= 1111
0
0
0
0
0
0
STRB{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>{, LSL #<imm>}]
STRB{<c>}.W <Rt>, [<Rn>, {+}<Rm>]
if Rn == '1111' then Undefined(); end;
let t : integer = UInt(Rt);
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let index : boolean = TRUE;
let add : boolean = TRUE;
let wback : boolean = FALSE;
let shift_t : SRType = SRType_LSL;
let shift_n : integer = UInt(imm2);
// Armv8-A removes UNPREDICTABLE for R13
if t == 15 || m == 15 then UnpredictableProcedure(); end;
t == 15
The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is UNKNOWN.
<c>
See Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Rt>
Is the general-purpose register to be transferred, encoded in the "Rt" field.
<Rn>
For the "A1 Offset", "A1 Post-indexed", and "A1 Pre-indexed" variants: is the general-purpose base register, encoded in the "Rn" field. The PC can be used in the offset variant, but this is deprecated.
<Rn>
For the "T1" and "T2" variants: is the general-purpose base register, encoded in the "Rn" field.
+/-
Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and
<Rm>
Is the general-purpose index register, encoded in the "Rm" field.
<shift>
The shift to apply to the value read from <Rm>. If absent, no shift is applied. Otherwise, see Shifts applied to a register.
+
Specifies the index register is added to the base register.
<imm>
If present, the size of the left shift to apply to the value from <Rm>, in the range 1-3. <imm> is encoded in imm2. If absent, no shift is specified and imm2 is encoded as 0b00.
if ConditionPassed() then
EncodingSpecificOperations();
let offset : bits(32) = Shift{}(R(m), shift_t, shift_n, PSTATE.C);
let offset_addr : bits(32) = if add then (R(n) + offset) else (R(n) - offset);
let address : bits(32) = if index then offset_addr else R(n);
MemU{8}(address) = R(t)[7:0];
if wback then R(n) = offset_addr; end;
end;
2026-03-26 20:27:25
2026-03_rel