STRH (immediate)
Store Register Halfword (immediate)
Store Register Halfword (immediate) calculates an address from a
base register value and an immediate offset, and stores a halfword
from a register to memory. It can use offset, post-indexed, or
pre-indexed addressing. For information about memory accesses see
Memory accesses.
For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
,
T2
and
T3
)
.
!= 1111
0
0
0
1
0
1
0
1
1
1
0
STRH{<c>}{<q>} <Rt>, [<Rn> {, #{+/-}<imm>}]
0
0
STRH{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm>
1
1
STRH{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<imm>]!
if P == '0' && W == '1' then See("STRHT"); end;
let t : integer = UInt(Rt);
let n : integer = UInt(Rn);
let imm32 : bits(32) = ZeroExtend{}(imm4H::imm4L);
let index : boolean = (P == '1');
let add : boolean = (U == '1');
let wback : boolean = (P == '0') || (W == '1');
if t == 15 then UnpredictableProcedure(); end;
if wback && (n == 15 || n == t) then UnpredictableProcedure(); end;
t == 15
The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is UNKNOWN.
wback && n == t
wback && n == 15
The instruction uses the addressing mode described in the equivalent immediate offset instruction.
1
0
0
0
0
STRH{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}]
let t : integer = UInt(Rt);
let n : integer = UInt(Rn);
let imm32 : bits(32) = ZeroExtend{}(imm5::'0');
let index : boolean = TRUE;
let add : boolean = TRUE;
let wback : boolean = FALSE;
1
1
1
1
1
0
0
0
1
0
1
0
!= 1111
STRH{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}]
STRH{<c>}.W <Rt>, [<Rn> {, #{+}<imm>}]
if Rn == '1111' then Undefined(); end;
let t : integer = UInt(Rt);
let n : integer = UInt(Rn);
let imm32 : bits(32) = ZeroExtend{}(imm12);
let index : boolean = TRUE;
let add : boolean = TRUE;
let wback : boolean = FALSE;
// Armv8-A removes UNPREDICTABLE for R13
if t == 15 then UnpredictableProcedure(); end;
t == 15
The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is UNKNOWN.
1
1
1
1
1
0
0
0
0
0
1
0
!= 1111
1
1
0
0
STRH{<c>}{<q>} <Rt>, [<Rn> {, #-<imm>}]
0
1
STRH{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm>
1
1
STRH{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<imm>]!
if P == '1' && U == '1' && W == '0' then See("STRHT"); end;
if Rn == '1111' || (P == '0' && W == '0') then Undefined(); end;
let t : integer = UInt(Rt);
let n : integer = UInt(Rn);
let imm32 : bits(32) = ZeroExtend{}(imm8);
let index : boolean = (P == '1');
let add : boolean = (U == '1');
let wback : boolean = (W == '1');
// Armv8-A removes UNPREDICTABLE for R13
if t == 15 || (wback && n == t) then UnpredictableProcedure(); end;
t == 15
The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is UNKNOWN.
wback && n == t
<c>
See Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Rt>
Is the general-purpose register to be transferred, encoded in the "Rt" field.
<Rn>
For the "A1 Offset" variant: is the general-purpose base register, encoded in the "Rn" field. The PC can be used in the offset variant, but this is deprecated.
<Rn>
For the "A1 Post-indexed", "A1 Pre-indexed", "T1", "T2", "T3 Offset", "T3 Post-indexed", and "T3 Pre-indexed" variants: is the general-purpose base register, encoded in the "Rn" field.
+/-
Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
<imm>
For the "A1 Offset", "A1 Post-indexed", and "A1 Pre-indexed" variants: is the 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm4H:imm4L" field.
<imm>
For the "T1" variant: is the optional positive unsigned immediate byte offset, a multiple of 2, in the range 0 to 62, defaulting to 0 and encoded in the "imm5" field as <imm>/2.
<imm>
For the "T2" variant: is an optional 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.
<imm>
For the "T3 Offset", "T3 Post-indexed", and "T3 Pre-indexed" variants: is an 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm8" field.
+
Specifies the offset is added to the base register.
if CurrentInstrSet() == InstrSet_A32 then
if ConditionPassed() then
EncodingSpecificOperations();
let offset_addr : bits(32) = if add then (R(n) + imm32) else (R(n) - imm32);
let address : bits(32) = if index then offset_addr else R(n);
MemU{16}(address) = R(t)[15:0];
if wback then R(n) = offset_addr; end;
end;
else
if ConditionPassed() then
EncodingSpecificOperations();
let offset_addr : bits(32) = if add then (R(n) + imm32) else (R(n) - imm32);
let address : bits(32) = if index then offset_addr else R(n);
MemU{16}(address) = R(t)[15:0];
if wback then R(n) = offset_addr; end;
end;
end;
2026-03-26 20:27:25
2026-03_rel