SVC Supervisor Call Supervisor Call causes a Supervisor Call exception. For more information, see Supervisor Call (SVC) exception. SVC was previously called SWI, Software Interrupt, and this name is still found in some documentation. Software can use this instruction as a call to an operating system to provide a service. In the following cases, the Supervisor Call exception generated by the SVC instruction is taken to Hyp mode: If the SVC is executed in Hyp mode. If HCR.TGE is set to 1, and the SVC is executed in Non-secure User mode. For more information, see Supervisor Call exception, when HCR.TGE is set to 1 In these cases, the HSR, Hyp Syndrome Register identifies that the exception entry was caused by a Supervisor Call exception, EC value 0x11, see Use of the HSR. The immediate field in the HSR: If the SVC is unconditional: For the T32 instruction, is the zero-extended value of the imm8 field. For the A32 instruction, is the least-significant 16 bits the imm24 field. If the SVC is conditional, is UNKNOWN. It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) . != 1111 1 1 1 1 SVC{<c>}{<q>} {#}<imm> let imm32 : bits(32) = ZeroExtend{}(imm24); 1 1 0 1 1 1 1 1 SVC{<c>}{<q>} {#}<imm> let imm32 : bits(32) = ZeroExtend{}(imm8); <c> See Standard assembler syntax fields. <q> See Standard assembler syntax fields. <imm> For the "A1" variant: is a 24-bit unsigned immediate, in the range 0 to 16777215, encoded in the "imm24" field. This value is for assembly and disassembly only. SVC handlers in some systems interpret imm24 in software, for example to determine the required service. <imm> For the "T1" variant: is a 8-bit unsigned immediate, in the range 0 to 255, encoded in the "imm8" field. This value is for assembly and disassembly only. SVC handlers in some systems interpret imm8 in software, for example to determine the required service. if ConditionPassed() then EncodingSpecificOperations(); AArch32_CheckForSVCTrap(imm32[15:0]); AArch32_CallSupervisor(imm32[15:0]); end; 2026-03-26 20:27:25 2026-03_rel