Unconditional branch

111 00

16-bit

!= 111 != 111xxx

Shift (immediate), add, subtract, move, and compare

00xxxx 0 0

Add, subtract (three low registers)

0 11 0

Add, subtract (two low registers and immediate)

0 11 1

Shift (immediate)

0 != 11

Add, subtract, compare, move (one low register and immediate)

1

Data-processing (two low registers)

010000

Special data instructions and branch and exchange

010001 0 1 0 0 0 1

Branch and exchange

11

Add, subtract, compare, move (two high registers)

!= 11

Load literal

01001x

Load/store (register offset)

0101xx

Load/store word/byte (immediate offset)

011xxx

Load/store halfword (immediate offset)

1000xx

Load/store (SP-relative)

1001xx

Add PC/SP (immediate)

1010xx

Miscellaneous 16-bit instructions

1011xx 1 0 1 1

Adjust SP (immediate)

0000

Extend

0010

SETPAN

0110 00 0

UNALLOCATED

0110 00 1

Change Processor State

0110 01

UNALLOCATED

0110 1x

UNALLOCATED

0111

UNALLOCATED

1000

Halting breakpoint

1010 10

Reverse bytes

1010 != 10

Software breakpoint

1110

Hints

1111 0000

If-Then

1111 != 0000

Compare and branch zero/non-zero

x0x1

Push and Pop

x10x

Load/store multiple

1100xx

Conditional branch, and Supervisor Call

1101xx 1 1 0 1

Exception generation

111x

Conditional branch

!= 111x

32-bit

111 != 00 1 1 1 != 00xx

Load/store multiple

0100 xx0xx

Load/store dual, load/store exclusive, load-acquire/store-release, and table branch

0100 xx1xx 1 1 1 0 1 0 0 x x 1 x

Load/store exclusive

0010

UNALLOCATED

0110 0 00x

Table branch

0110 1 000

UNALLOCATED

0110 1 001

Load/store exclusive byte/half/dual

0110 01x

Load-acquire / Store-release

0110 1xx

Load dual (literal)

0x11 1111

Load/store dual (immediate, post-indexed)

0x11 != 1111

Load/store dual (immediate)

1x10 != 1111

Load/store dual (immediate, pre-indexed)

1x11 != 1111

Load dual (literal)

1x1x 1111

Data-processing (shifted register)

0101

Data-processing (modified immediate)

10x0 0

Data-processing (plain binary immediate)

10x1 xxxx0 0 1 1 1 1 0 1 0 0

Data-processing (simple immediate)

0 0x

Move Wide (16-bit immediate)

0 10

UNALLOCATED

0 11

Saturate, Bitfield

1

UNALLOCATED

10x1 xxxx1 0

Branches and miscellaneous control

10xx 1 1 1 1 1 0 1

MSR (special)

0 1110 0x 0x0 0

MSR (banked)

0 1110 0x 0x0 1

Hints

0 1110 10 0x0 000

Change processor state

0 1110 10 0x0 != 000

Miscellaneous system

0 1110 11 0x0

Branch and Exchange Jazelle

0 1111 00 0x0

Exception return

0 1111 01 0x0

MRS (special)

0 1111 1x 0x0 0

MRS (banked)

0 1111 1x 0x0 1

DCPS

1 1110 00 000

UNALLOCATED

1 1110 00 010

UNALLOCATED

1 1110 != 00 0x0

UNALLOCATED

1 1111 0x 0x0

Exception generation

1 1111 1x 0x0

Unconditional branch

0x1

Unconditional branch and link exchange

1x0

Unconditional branch and link

1x1

Conditional branch

!= 111x 0x0

Advanced SIMD element or structure load/store

1100 1xxx0 1 1 1 1 1 0 0 1 0

Advanced SIMD load/store multiple structures

0

Advanced SIMD load single structure to all lanes

1 11

Advanced SIMD load/store single structure to one lane

1 != 11

Load/store single

1100 != 1xxx0 1 1 1 1 1 0 0

Load/store, unsigned (register offset)

00 != 1111 000000

UNALLOCATED

00 != 1111 000001

UNALLOCATED

00 != 1111 00001x

UNALLOCATED

00 != 1111 0001xx

UNALLOCATED

00 != 1111 001xxx

UNALLOCATED

00 != 1111 01xxxx

UNALLOCATED

00 != 1111 10x0xx

Load/store, unsigned (immediate, post-indexed)

00 != 1111 10x1xx

Load/store, unsigned (negative immediate)

00 != 1111 1100xx

Load/store, unsigned (unprivileged)

00 != 1111 1110xx

Load/store, unsigned (immediate, pre-indexed)

00 != 1111 11x1xx

Load/store, unsigned (positive immediate)

01 != 1111

Load, unsigned (literal)

0x 1111

Load/store, signed (register offset)

10 1 != 1111 000000

UNALLOCATED

10 1 != 1111 000001

UNALLOCATED

10 1 != 1111 00001x

UNALLOCATED

10 1 != 1111 0001xx

UNALLOCATED

10 1 != 1111 001xxx

UNALLOCATED

10 1 != 1111 01xxxx

UNALLOCATED

10 1 != 1111 10x0xx

Load/store, signed (immediate, post-indexed)

10 1 != 1111 10x1xx

Load/store, signed (negative immediate)

10 1 != 1111 1100xx

Load/store, signed (unprivileged)

10 1 != 1111 1110xx

Load/store, signed (immediate, pre-indexed)

10 1 != 1111 11x1xx

Load/store, signed (positive immediate)

11 1 != 1111

Load, signed (literal)

1x 1 1111

Data-processing (register)

1101 0xxxx 1 1 1 1 1 0 1 0

Register shifts

0 1111 0000

UNALLOCATED

0 1111 0001

UNALLOCATED

0 1111 001x

UNALLOCATED

0 1111 01xx

Register extends

0 1111 1xxx

Parallel add-subtract

1 1111 0xxx

Data-processing (two source registers)

1 1111 10xx

UNALLOCATED

1 1111 11xx

UNALLOCATED

!= 1111

Multiply, multiply accumulate, and absolute difference

1101 10xxx 1 1 1 1 1 0 1 1 0

Multiply and absolute difference

00

UNALLOCATED

!= 00

Long multiply and divide

1101 11xxx 1 1 1 1 1 0 1 1 1

Divide

0x1

Long Multiply

!= 0x1

System register access, Advanced SIMD, and floating-point

x11x 1 1 1 1 1

Advanced SIMD and System register load/store and 64-bit move

0 0x 1x 1 1 1 0 1 1 0 1

Advanced SIMD and floating-point 64-bit move

00x0 0x

System register 64-bit move

00x0 11

UNALLOCATED

10

Advanced SIMD and floating-point load/store

!= 00x0 0x

System register Load/Store

!= 00x0 11

Floating-point data-processing

0 10 10 0 1 1 1 0 1 1 1 0 1 0 0

Floating-point move immediate

1x11 0

Floating-point data-processing (two registers)

1x11 1

Floating-point data-processing (three registers)

!= 1x11

UNALLOCATED

0 10 11 0

Advanced SIMD and System register 32-bit move

0 10 1x 1 1 1 1 0 1 1 1 0 1 1

UNALLOCATED

000 000

Floating-point 16-bit move

000 001

Floating-point 32-bit move

000 010

UNALLOCATED

000 10x

UNALLOCATED

0x1 010

UNALLOCATED

10x 010

Floating-point move special register

111 010

UNALLOCATED

x10 010

Advanced SIMD 8/16/32-bit element move/duplicate

011

System register 32-bit move

11x

UNALLOCATED

!= 000 x0x

Additional Advanced SIMD and floating-point instructions

1 != 11 1x 1 1 1 1 1 1 != 11x 1

Advanced SIMD three registers of the same length extension

0xx 0x

UNALLOCATED

0xx 1x

Floating-point conditional select

100 0 != 00 0 0

UNALLOCATED

100 0 != 00 1 0

Floating-point minNum/maxNum

101 00xxxx 0 != 00 0

UNALLOCATED

101 01xxxx 0 != 00 0

UNALLOCATED

101 10xxxx 0 != 00 0

Floating-point extraction and insertion

101 110000 0 != 00 1 0

UNALLOCATED

101 110001 0 != 00 1 0

UNALLOCATED

101 11001x 0 != 00 1 0

UNALLOCATED

101 1101xx 0 != 00 1 0

Floating-point directed convert to integer

101 111xxx 0 != 00 1 0

UNALLOCATED

101 11xxxx 0 != 00 0 0

Advanced SIMD and floating-point multiply with accumulate

10x 0 00

UNALLOCATED

10x 0 != 00 1

Advanced SIMD and floating-point dot product

10x 1 0x

UNALLOCATED

10x 1 1x

Advanced SIMD data-processing

11 1 1 1 1 1 1 1

Advanced SIMD three registers of the same length

0

Advanced SIMD two registers, or three registers of different lengths

1 0 1 1 1 1 1 1 1 1 0

Advanced SIMD vector extract

0 11

Advanced SIMD two registers misc

1 11 0x

Advanced SIMD table permute

1 11 10

Advanced SIMD duplicate (scalar)

1 11 11

Advanced SIMD three registers of different lengths

!= 11 0

Advanced SIMD two registers and a scalar

!= 11 1

Advanced SIMD shifts and immediate generation

1 1 1 1 1 1 1 1 1 1 1

Advanced SIMD one register and modified immediate

000xxxxxxxxxxx0

Advanced SIMD two registers and shift amount

!= 000xxxxxxxxxxx0

UNALLOCATED

!= 11 0x Instruction bits Encoding Group 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unconditional branch 111 != 00 32-bit 16-bit Instruction bits Instruction class 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 x11x System register access, Advanced SIMD, and floating-point 1 1 1 0100 xx0xx Load/store multiple 1 1 1 0100 xx1xx Load/store dual, load/store exclusive, load-acquire/store-release, and table branch 1 1 1 0101 Data-processing (shifted register) 1 1 1 10xx 1 Branches and miscellaneous control 1 1 1 10x0 0 Data-processing (modified immediate) 1 1 1 10x1 xxxx0 0 Data-processing (plain binary immediate) 1 1 1 1100 1xxx0 Advanced SIMD element or structure load/store 1 1 1 1100 != 1xxx0 Load/store single 1 1 1 1101 0xxxx Data-processing (register) 1 1 1 1101 10xxx Multiply, multiply accumulate, and absolute difference 1 1 1 1101 11xxx Long multiply and divide 00xxxx Shift (immediate), add, subtract, move, and compare 010000 Data-processing (two low registers) 010001 Special data instructions and branch and exchange 01001x Load literal 0101xx Load/store (register offset) 011xxx Load/store word/byte (immediate offset) 1000xx Load/store halfword (immediate offset) 1001xx Load/store (SP-relative) 1010xx Add PC/SP (immediate) 1011xx Miscellaneous 16-bit instructions 1100xx Load/store multiple 1101xx Conditional branch, and Supervisor Call 16-bit 1 0 1 0 Decode fields Instruction page Encoding SP 0 ADR T1 1 ADD, ADDS (SP plus immediate) T1 1 1 0 1 1 1 1 Decode fields Instruction page Encoding S 0 UDF T1 1 SVC T1 1 1 0 1 != 111x Instruction page Encoding B T1 0 1 0 0 0 0 Decode fields Instruction page Encoding op 0000 AND, ANDS (register) T1 0001 EOR, EORS (register) T1 0010 MOV, MOVS (register-shifted register) Logical shift left 0011 MOV, MOVS (register-shifted register) Logical shift right 0100 MOV, MOVS (register-shifted register) Arithmetic shift right 0101 ADC, ADCS (register) T1 0110 SBC, SBCS (register) T1 0111 MOV, MOVS (register-shifted register) Rotate right 1000 TST (register) T1 1001 RSB, RSBS (immediate) T1 1010 CMP (register) T1 1011 CMN (register) T1 1100 ORR, ORRS (register) T1 1101 MUL, MULS T1 1110 BIC, BICS (register) T1 1111 MVN, MVNS (register) T1 0 1 0 0 1 Instruction page Encoding LDR (literal) T1 1 0 0 1 Decode fields Instruction page Encoding L 0 STR (immediate) T2 1 LDR (immediate) T2 0 1 0 1 Decode fields Instruction page Encoding L B H 0 0 0 STR (register) T1 0 0 1 STRH (register) T1 0 1 0 STRB (register) T1 0 1 1 LDRSB (register) T1 1 0 0 LDR (register) T1 1 0 1 LDRH (register) T1 1 1 0 LDRB (register) T1 1 1 1 LDRSH (register) T1 1 0 0 0 Decode fields Instruction page Encoding L 0 STRH (immediate) T1 1 LDRH (immediate) T1 1 1 0 0 Decode fields Instruction page Encoding L 0 STM, STMIA, STMEA T1 1 LDM, LDMIA, LDMFD T1 0 1 1 Decode fields Instruction page Encoding B L 0 0 STR (immediate) T1 0 1 LDR (immediate) T1 1 0 STRB (immediate) T1 1 1 LDRB (immediate) T1 1 0 1 1 0 0 0 0 Decode fields Instruction page Encoding S 0 ADD, ADDS (SP plus immediate) T2 1 SUB, SUBS (SP minus immediate) T1 1 0 1 1 0 0 1 0 Decode fields Instruction page Encoding U B 0 0 SXTH T1 0 1 SXTB T1 1 0 UXTH T1 1 1 UXTB T1 1 0 1 1 0 1 1 0 0 0 0 (1) (0) (0) (0) Instruction page Encoding SETPAN T1 1 0 1 1 0 1 1 0 0 1 Decode fields Instruction page Encoding op flags 0 SETEND T1 1 0xxxx CPS, CPSID, CPSIE Interrupt enable 1 1xxxx CPS, CPSID, CPSIE Interrupt disable 1 0 1 1 1 0 1 0 1 0 Instruction page Encoding HLT T1 1 0 1 1 1 0 1 0 != 10 Decode fields Instruction page Encoding op 00 REV T1 01 REV16 T1 11 REVSH T1 1 0 1 1 1 1 1 0 Instruction page Encoding BKPT T1 1 0 1 1 1 1 1 1 0 0 0 0 Decode fields Instruction page Encoding hint 0000 NOP T1 0001 YIELD T1 0010 WFE T1 0011 WFI T1 0100 SEV T1 0101 SEVL T1 011x Reserved hint, behaves as NOP 1xxx Reserved hint, behaves as NOP 1 0 1 1 1 1 1 1 != 0000 Instruction page Encoding IT 1 0 1 1 0 1 Decode fields Instruction page Encoding op 0 CBNZ, CBZ CBZ 1 CBNZ, CBZ CBNZ 1 0 1 1 1 0 Decode fields Instruction page Encoding L 0 PUSH 1 POP 0 0 0 1 1 0 Decode fields Instruction page Encoding S 0 ADD, ADDS (register) T1 1 SUB, SUBS (register) T1 0 0 0 1 1 1 Decode fields Instruction page Encoding S 0 ADD, ADDS (immediate) T1 1 SUB, SUBS (immediate) T1 0 0 0 != 11 Instruction page Encoding MOV, MOVS (register) T2 0 0 1 Decode fields Instruction page Encoding op 00 MOV, MOVS (immediate) T1 01 CMP (immediate) T1 10 ADD, ADDS (immediate) T2 11 SUB, SUBS (immediate) T2 0 1 0 0 0 1 1 1 (0) (0) (0) Decode fields Instruction page Encoding L 0 BX T1 1 BLX (register) T1 0 1 0 0 0 1 != 11 Decode fields Instruction page Encoding op D:Rd Rs 00 1101 ADD, ADDS (SP plus register) T1 00 1101 != 1101 ADD, ADDS (SP plus register) T2 00 != 1101 != 1101 ADD, ADDS (register) T2 01 CMP (register) T2 10 MOV, MOVS (register) T1 Unconditional branch 1 1 1 0 0 Instruction page Encoding B T2 32-bit 1 1 1 1 1 0 0 1 0 0 Decode fields Instruction page Encoding L itype Rm 1011 UNALLOCATED 11xx UNALLOCATED 0 000x 1101 VST4 (multiple 4-element structures) Post-indexed 0 000x 1111 VST4 (multiple 4-element structures) Offset 0 000x != 11x1 VST4 (multiple 4-element structures) Post-indexed 0 0010 1101 VST1 (multiple single elements) Post-indexed 0 0010 1111 VST1 (multiple single elements) Offset 0 0010 != 11x1 VST1 (multiple single elements) Post-indexed 0 0011 1101 VST2 (multiple 2-element structures) Post-indexed 0 0011 1111 VST2 (multiple 2-element structures) Offset 0 0011 != 11x1 VST2 (multiple 2-element structures) Post-indexed 0 010x 1101 VST3 (multiple 3-element structures) Post-indexed 0 010x 1111 VST3 (multiple 3-element structures) Offset 0 010x != 11x1 VST3 (multiple 3-element structures) Post-indexed 0 0110 1101 VST1 (multiple single elements) Post-indexed 0 0110 1111 VST1 (multiple single elements) Offset 0 0110 != 11x1 VST1 (multiple single elements) Post-indexed 0 0111 1101 VST1 (multiple single elements) Post-indexed 0 0111 1111 VST1 (multiple single elements) Offset 0 0111 != 11x1 VST1 (multiple single elements) Post-indexed 0 100x 1101 VST2 (multiple 2-element structures) Post-indexed 0 100x 1111 VST2 (multiple 2-element structures) Offset 0 100x != 11x1 VST2 (multiple 2-element structures) Post-indexed 0 1010 1101 VST1 (multiple single elements) Post-indexed 0 1010 1111 VST1 (multiple single elements) Offset 0 1010 != 11x1 VST1 (multiple single elements) Post-indexed 1 000x 1101 VLD4 (multiple 4-element structures) Post-indexed 1 000x 1111 VLD4 (multiple 4-element structures) Offset 1 000x != 11x1 VLD4 (multiple 4-element structures) Post-indexed 1 0010 1101 VLD1 (multiple single elements) Post-indexed 1 0010 1111 VLD1 (multiple single elements) Offset 1 0010 != 11x1 VLD1 (multiple single elements) Post-indexed 1 0011 1101 VLD2 (multiple 2-element structures) Post-indexed 1 0011 1111 VLD2 (multiple 2-element structures) Offset 1 0011 != 11x1 VLD2 (multiple 2-element structures) Post-indexed 1 010x 1101 VLD3 (multiple 3-element structures) Post-indexed 1 010x 1111 VLD3 (multiple 3-element structures) Offset 1 010x != 11x1 VLD3 (multiple 3-element structures) Post-indexed 1 0110 1101 VLD1 (multiple single elements) Post-indexed 1 0110 1111 VLD1 (multiple single elements) Offset 1 0110 != 11x1 VLD1 (multiple single elements) Post-indexed 1 0111 1101 VLD1 (multiple single elements) Post-indexed 1 0111 1111 VLD1 (multiple single elements) Offset 1 0111 != 11x1 VLD1 (multiple single elements) Post-indexed 1 100x 1101 VLD2 (multiple 2-element structures) Post-indexed 1 100x 1111 VLD2 (multiple 2-element structures) Offset 1 100x != 11x1 VLD2 (multiple 2-element structures) Post-indexed 1 1010 1101 VLD1 (multiple single elements) Post-indexed 1 1010 1111 VLD1 (multiple single elements) Offset 1 1010 != 11x1 VLD1 (multiple single elements) Post-indexed 1 1 1 1 1 0 0 1 1 0 1 1 Decode fields Instruction page Encoding L N a Rm 0 UNALLOCATED 1 00 1101 VLD1 (single element to all lanes) Post-indexed 1 00 1111 VLD1 (single element to all lanes) Offset 1 00 != 11x1 VLD1 (single element to all lanes) Post-indexed 1 01 1101 VLD2 (single 2-element structure to all lanes) Post-indexed 1 01 1111 VLD2 (single 2-element structure to all lanes) Offset 1 01 != 11x1 VLD2 (single 2-element structure to all lanes) Post-indexed 1 10 0 1101 VLD3 (single 3-element structure to all lanes) Post-indexed 1 10 0 1111 VLD3 (single 3-element structure to all lanes) Offset 1 10 0 != 11x1 VLD3 (single 3-element structure to all lanes) Post-indexed 1 10 1 UNALLOCATED 1 11 1101 VLD4 (single 4-element structure to all lanes) Post-indexed 1 11 1111 VLD4 (single 4-element structure to all lanes) Offset 1 11 != 11x1 VLD4 (single 4-element structure to all lanes) Post-indexed 1 1 1 1 1 0 0 1 1 0 != 11 Decode fields Instruction page Encoding L size N Rm 0 00 00 1101 VST1 (single element from one lane) Post-indexed 0 00 00 1111 VST1 (single element from one lane) Offset 0 00 00 != 11x1 VST1 (single element from one lane) Post-indexed 0 00 01 1101 VST2 (single 2-element structure from one lane) Post-indexed 0 00 01 1111 VST2 (single 2-element structure from one lane) Offset 0 00 01 != 11x1 VST2 (single 2-element structure from one lane) Post-indexed 0 00 10 1101 VST3 (single 3-element structure from one lane) Post-indexed 0 00 10 1111 VST3 (single 3-element structure from one lane) Offset 0 00 10 != 11x1 VST3 (single 3-element structure from one lane) Post-indexed 0 00 11 1101 VST4 (single 4-element structure from one lane) Post-indexed 0 00 11 1111 VST4 (single 4-element structure from one lane) Offset 0 00 11 != 11x1 VST4 (single 4-element structure from one lane) Post-indexed 0 01 00 1101 VST1 (single element from one lane) Post-indexed 0 01 00 1111 VST1 (single element from one lane) Offset 0 01 00 != 11x1 VST1 (single element from one lane) Post-indexed 0 01 01 1101 VST2 (single 2-element structure from one lane) Post-indexed 0 01 01 1111 VST2 (single 2-element structure from one lane) Offset 0 01 01 != 11x1 VST2 (single 2-element structure from one lane) Post-indexed 0 01 10 1101 VST3 (single 3-element structure from one lane) Post-indexed 0 01 10 1111 VST3 (single 3-element structure from one lane) Offset 0 01 10 != 11x1 VST3 (single 3-element structure from one lane) Post-indexed 0 01 11 1101 VST4 (single 4-element structure from one lane) Post-indexed 0 01 11 1111 VST4 (single 4-element structure from one lane) Offset 0 01 11 != 11x1 VST4 (single 4-element structure from one lane) Post-indexed 0 10 00 1101 VST1 (single element from one lane) Post-indexed 0 10 00 1111 VST1 (single element from one lane) Offset 0 10 00 != 11x1 VST1 (single element from one lane) Post-indexed 0 10 01 1101 VST2 (single 2-element structure from one lane) Post-indexed 0 10 01 1111 VST2 (single 2-element structure from one lane) Offset 0 10 01 != 11x1 VST2 (single 2-element structure from one lane) Post-indexed 0 10 10 1101 VST3 (single 3-element structure from one lane) Post-indexed 0 10 10 1111 VST3 (single 3-element structure from one lane) Offset 0 10 10 != 11x1 VST3 (single 3-element structure from one lane) Post-indexed 0 10 11 1101 VST4 (single 4-element structure from one lane) Post-indexed 0 10 11 1111 VST4 (single 4-element structure from one lane) Offset 0 10 11 != 11x1 VST4 (single 4-element structure from one lane) Post-indexed 1 00 00 1101 VLD1 (single element to one lane) Post-indexed 1 00 00 1111 VLD1 (single element to one lane) Offset 1 00 00 != 11x1 VLD1 (single element to one lane) Post-indexed 1 00 01 1101 VLD2 (single 2-element structure to one lane) Post-indexed 1 00 01 1111 VLD2 (single 2-element structure to one lane) Offset 1 00 01 != 11x1 VLD2 (single 2-element structure to one lane) Post-indexed 1 00 10 1101 VLD3 (single 3-element structure to one lane) Post-indexed 1 00 10 1111 VLD3 (single 3-element structure to one lane) Offset 1 00 10 != 11x1 VLD3 (single 3-element structure to one lane) Post-indexed 1 00 11 1101 VLD4 (single 4-element structure to one lane) Post-indexed 1 00 11 1111 VLD4 (single 4-element structure to one lane) Offset 1 00 11 != 11x1 VLD4 (single 4-element structure to one lane) Post-indexed 1 01 00 1101 VLD1 (single element to one lane) Post-indexed 1 01 00 1111 VLD1 (single element to one lane) Offset 1 01 00 != 11x1 VLD1 (single element to one lane) Post-indexed 1 01 01 1101 VLD2 (single 2-element structure to one lane) Post-indexed 1 01 01 1111 VLD2 (single 2-element structure to one lane) Offset 1 01 01 != 11x1 VLD2 (single 2-element structure to one lane) Post-indexed 1 01 10 1101 VLD3 (single 3-element structure to one lane) Post-indexed 1 01 10 1111 VLD3 (single 3-element structure to one lane) Offset 1 01 10 != 11x1 VLD3 (single 3-element structure to one lane) Post-indexed 1 01 11 1101 VLD4 (single 4-element structure to one lane) Post-indexed 1 01 11 1111 VLD4 (single 4-element structure to one lane) Offset 1 01 11 != 11x1 VLD4 (single 4-element structure to one lane) Post-indexed 1 10 00 1101 VLD1 (single element to one lane) Post-indexed 1 10 00 1111 VLD1 (single element to one lane) Offset 1 10 00 != 11x1 VLD1 (single element to one lane) Post-indexed 1 10 01 1101 VLD2 (single 2-element structure to one lane) Post-indexed 1 10 01 1111 VLD2 (single 2-element structure to one lane) Offset 1 10 01 != 11x1 VLD2 (single 2-element structure to one lane) Post-indexed 1 10 10 1101 VLD3 (single 3-element structure to one lane) Post-indexed 1 10 10 1111 VLD3 (single 3-element structure to one lane) Offset 1 10 10 != 11x1 VLD3 (single 3-element structure to one lane) Post-indexed 1 10 11 1101 VLD4 (single 4-element structure to one lane) Post-indexed 1 10 11 1111 VLD4 (single 4-element structure to one lane) Offset 1 10 11 != 11x1 VLD4 (single 4-element structure to one lane) Post-indexed 1 1 1 1 0 0 1 1 1 0 0 1 0 (0) 0 (0) (0) 0 (0) (0) (0) (0) (0) Instruction page Encoding MSR (register) T1 1 1 1 1 0 0 1 1 1 0 0 1 0 (0) 0 (0) (0) 1 (0) (0) (0) (0) Instruction page Encoding MSR (Banked register) T1 1 1 1 1 0 0 1 1 1 0 1 0 (1) (1) (1) (1) 1 0 (0) 0 (0) 0 0 0 Decode fields Instruction page Encoding hint option x101 Reserved hint, behaves as NOP 0x1x Reserved hint, behaves as NOP 000x 1xxx Reserved hint, behaves as NOP 0000 0000 NOP T2 0000 0001 YIELD T2 0000 0010 WFE T2 0000 0011 WFI T2 0000 0100 SEV T2 0000 0101 SEVL T2 0000 011x Reserved hint, behaves as NOP 0001 0xx1 Reserved hint, behaves as NOP 0001 0000 ESB T1 0001 0010 TSB T1 0001 0100 CSDB T1 0001 0110 CLRBHB T1 0100 Reserved hint, behaves as NOP 10xx Reserved hint, behaves as NOP 11x0 Reserved hint, behaves as NOP 1111 DBG T1 1 1 1 1 0 0 1 1 1 0 1 0 (1) (1) (1) (1) 1 0 (0) 0 (0) Decode fields Instruction page Encoding imod M 00 1 CPS, CPSID, CPSIE Change mode 01 UNALLOCATED 10 0 CPS, CPSID, CPSIE Interrupt enable 10 1 CPS, CPSID, CPSIE Interrupt enable and change mode 11 0 CPS, CPSID, CPSIE Interrupt disable 11 1 CPS, CPSID, CPSIE Interrupt disable and change mode 1 1 1 1 0 0 1 1 1 0 1 1 (1) (1) (1) (1) 1 0 (0) 0 (1) (1) (1) (1) Decode fields Instruction page Encoding opc option 000x UNALLOCATED 0010 CLREX T1 0011 UNALLOCATED 0100 0000 SSBB T1 0100 0100 PSSBB T1 0100 != 0x00 DSB T1 0101 DMB T1 0110 ISB T1 0111 SB T1 1xxx UNALLOCATED 1 1 1 1 0 0 1 1 1 1 0 0 1 0 (0) 0 (1) (1) (1) (1) (0) (0) (0) (0) (0) (0) (0) (0) Instruction page Encoding BXJ T1 1 1 1 1 0 0 1 1 1 1 0 1 1 0 (0) 0 (1) (1) (1) (1) Decode fields Instruction page Encoding Rn:imm8 111000000000 ERET T1 != 111000000000 SUB, SUBS (immediate) T5 1 1 1 1 0 0 1 1 1 1 1 (1) (1) (1) (1) 1 0 (0) 0 (0) (0) 0 (0) (0) (0) (0) (0) Instruction page Encoding MRS T1 1 1 1 1 0 0 1 1 1 1 1 1 0 (0) 0 (0) (0) 1 (0) (0) (0) (0) Instruction page Encoding MRS (Banked register) T1 1 1 1 1 0 1 1 1 1 0 0 0 1 0 0 0 Decode fields Instruction page Encoding imm4 imm10 opt 1111 0000000000 00 UNALLOCATED 1111 0000000000 01 DCPS1 1111 0000000000 10 DCPS2 1111 0000000000 11 DCPS3 1111 != 0000000000 UNALLOCATED != 1111 UNALLOCATED 1 1 1 1 0 1 1 1 1 1 1 1 0 0 Decode fields Instruction page Encoding o1 o2 0 0 HVC T1 0 1 UNALLOCATED 1 0 SMC T1 1 1 UDF T2 1 1 1 1 0 != 111x 1 0 0 Instruction page Encoding B T3 1 1 1 1 0 1 0 1 Instruction page Encoding B T4 1 1 1 1 0 1 1 0 Instruction page Encoding BL, BLX (immediate) T2 1 1 1 1 0 1 1 1 Instruction page Encoding BL, BLX (immediate) T1 1 1 1 1 0 0 0 Decode fields Instruction page Encoding op1 S Rn Rd 0000 0 AND, ANDS (immediate) AND 0000 1 1111 TST (immediate) T1 0000 1 != 1111 AND, ANDS (immediate) ANDS 0001 0 BIC, BICS (immediate) BIC 0001 1 BIC, BICS (immediate) BICS 0010 0 1111 MOV, MOVS (immediate) MOV 0010 0 != 1111 ORR, ORRS (immediate) ORR 0010 1 1111 MOV, MOVS (immediate) MOVS 0010 1 != 1111 ORR, ORRS (immediate) ORRS 0011 0 1111 MVN, MVNS (immediate) MVN 0011 0 != 1111 ORN, ORNS (immediate) Not flag setting 0011 1 1111 MVN, MVNS (immediate) MVNS 0011 1 != 1111 ORN, ORNS (immediate) Flag setting 0100 0 EOR, EORS (immediate) EOR 0100 1 1111 TEQ (immediate) T1 0100 1 != 1111 EOR, EORS (immediate) EORS 0101 UNALLOCATED 011x UNALLOCATED 1000 0 1101 ADD, ADDS (SP plus immediate) ADD 1000 0 != 1101 ADD, ADDS (immediate) ADD 1000 1 1111 CMN (immediate) T1 1000 1 1101 != 1111 ADD, ADDS (SP plus immediate) ADDS 1000 1 != 1101 != 1111 ADD, ADDS (immediate) ADDS 1001 UNALLOCATED 1010 0 ADC, ADCS (immediate) ADC 1010 1 ADC, ADCS (immediate) ADCS 1011 0 SBC, SBCS (immediate) SBC 1011 1 SBC, SBCS (immediate) SBCS 1100 UNALLOCATED 1101 0 1101 SUB, SUBS (SP minus immediate) SUB 1101 0 != 1101 SUB, SUBS (immediate) SUB 1101 1 1111 CMP (immediate) T2 1101 1 1101 != 1111 SUB, SUBS (SP minus immediate) SUBS 1101 1 != 1101 != 1111 SUB, SUBS (immediate) SUBS 1110 0 RSB, RSBS (immediate) RSB 1110 1 RSB, RSBS (immediate) RSBS 1111 UNALLOCATED 1 1 1 1 0 1 0 0 0 0 Decode fields Instruction page Encoding o1 o2 Rn 0 0 1101 ADD, ADDS (SP plus immediate) T4 0 0 1111 ADR T3 0 0 != 11x1 ADD, ADDS (immediate) T4 0 1 UNALLOCATED 1 0 UNALLOCATED 1 1 1101 SUB, SUBS (SP minus immediate) T3 1 1 1111 ADR T2 1 1 != 11x1 SUB, SUBS (immediate) T4 1 1 1 1 0 1 0 1 0 0 0 Decode fields Instruction page Encoding o1 0 MOV, MOVS (immediate) T3 1 MOVT T1 1 1 1 1 0 (0) 1 1 0 0 (0) Decode fields Instruction page Encoding op1 Rn imm3:imm2 000 SSAT Logical shift left 001 00000 SSAT16 T1 001 != 00000 SSAT Arithmetic shift right 010 SBFX T1 011 1111 BFC T1 011 != 1111 BFI T1 100 USAT Logical shift left 101 00000 USAT16 T1 101 != 00000 USAT Arithmetic shift right 110 UBFX T1 111 UNALLOCATED 1 1 1 1 1 0 1 0 0 1 1 1 1 0 0 0 0 Decode fields Instruction page Encoding S 0 MOV, MOVS (register-shifted register) Not flag setting 1 MOV, MOVS (register-shifted register) Flag setting 1 1 1 1 1 0 1 0 0 1 1 1 1 1 (0) Decode fields Instruction page Encoding op1 U Rn 00 0 1111 SXTH T2 00 0 != 1111 SXTAH T1 00 1 1111 UXTH T2 00 1 != 1111 UXTAH T1 01 0 1111 SXTB16 T1 01 0 != 1111 SXTAB16 T1 01 1 1111 UXTB16 T1 01 1 != 1111 UXTAB16 T1 10 0 1111 SXTB T2 10 0 != 1111 SXTAB T1 10 1 1111 UXTB T2 10 1 != 1111 UXTAB T1 11 UNALLOCATED 1 1 1 1 1 0 1 0 1 1 1 1 1 0 Decode fields Instruction page Encoding op1 U H S x11 UNALLOCATED != x11 1 1 UNALLOCATED 000 0 0 0 SADD8 T1 000 0 0 1 QADD8 T1 000 0 1 0 SHADD8 T1 000 1 0 0 UADD8 T1 000 1 0 1 UQADD8 T1 000 1 1 0 UHADD8 T1 001 0 0 0 SADD16 T1 001 0 0 1 QADD16 T1 001 0 1 0 SHADD16 T1 001 1 0 0 UADD16 T1 001 1 0 1 UQADD16 T1 001 1 1 0 UHADD16 T1 010 0 0 0 SASX T1 010 0 0 1 QASX T1 010 0 1 0 SHASX T1 010 1 0 0 UASX T1 010 1 0 1 UQASX T1 010 1 1 0 UHASX T1 100 0 0 0 SSUB8 T1 100 0 0 1 QSUB8 T1 100 0 1 0 SHSUB8 T1 100 1 0 0 USUB8 T1 100 1 0 1 UQSUB8 T1 100 1 1 0 UHSUB8 T1 101 0 0 0 SSUB16 T1 101 0 0 1 QSUB16 T1 101 0 1 0 SHSUB16 T1 101 1 0 0 USUB16 T1 101 1 0 1 UQSUB16 T1 101 1 1 0 UHSUB16 T1 110 0 0 0 SSAX T1 110 0 0 1 QSAX T1 110 0 1 0 SHSAX T1 110 1 0 0 USAX T1 110 1 0 1 UQSAX T1 110 1 1 0 UHSAX T1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 0 Decode fields Instruction page Encoding op1 op2 000 00 QADD T1 000 01 QDADD T1 000 10 QSUB T1 000 11 QDSUB T1 001 00 REV T2 001 01 REV16 T2 001 10 RBIT T1 001 11 REVSH T2 01x != 00 UNALLOCATED 010 00 SEL T1 011 00 CLZ T1 100 00 CRC32 CRC32B 100 01 CRC32 CRC32H 100 10 CRC32 CRC32W 100 11 UNPREDICTABLE 101 00 CRC32C CRC32CB 101 01 CRC32C CRC32CH 101 10 CRC32C CRC32CW 101 11 UNPREDICTABLE 11x UNALLOCATED 1 1 1 0 1 0 1 (0) Decode fields Instruction page Encoding op1 S Rn imm3:imm2:stype Rd 0000 0 0000011 AND, ANDS (register) AND, rotate right with extend 0000 0 != 0000011 AND, ANDS (register) AND, shift or rotate by value 0000 1 0000011 1111 TST (register) Rotate right with extend 0000 1 0000011 != 1111 AND, ANDS (register) ANDS, rotate right with extend 0000 1 != 0000011 1111 TST (register) Shift or rotate by value 0000 1 != 0000011 != 1111 AND, ANDS (register) ANDS, shift or rotate by value 0001 0 0000011 BIC, BICS (register) BIC, rotate right with extend 0001 0 != 0000011 BIC, BICS (register) BIC, shift or rotate by value 0001 1 0000011 BIC, BICS (register) BICS, rotate right with extend 0001 1 != 0000011 BIC, BICS (register) BICS, shift or rotate by value 0010 0 1111 0000011 MOV, MOVS (register) MOV, rotate right with extend 0010 0 1111 != 0000011 MOV, MOVS (register) MOV, shift or rotate by value 0010 0 != 1111 0000011 ORR, ORRS (register) ORR, rotate right with extend 0010 0 != 1111 != 0000011 ORR, ORRS (register) ORR, shift or rotate by value 0010 1 1111 0000011 MOV, MOVS (register) MOVS, rotate right with extend 0010 1 1111 != 0000011 MOV, MOVS (register) MOVS, shift or rotate by value 0010 1 != 1111 0000011 ORR, ORRS (register) ORRS, rotate right with extend 0010 1 != 1111 != 0000011 ORR, ORRS (register) ORRS, shift or rotate by value 0011 0 1111 0000011 MVN, MVNS (register) MVN, rotate right with extend 0011 0 1111 != 0000011 MVN, MVNS (register) MVN, shift or rotate by value 0011 0 != 1111 0000011 ORN, ORNS (register) ORN, rotate right with extend 0011 0 != 1111 != 0000011 ORN, ORNS (register) ORN, shift or rotate by value 0011 1 1111 0000011 MVN, MVNS (register) MVNS, rotate right with extend 0011 1 1111 != 0000011 MVN, MVNS (register) MVNS, shift or rotate by value 0011 1 != 1111 0000011 ORN, ORNS (register) ORNS, rotate right with extend 0011 1 != 1111 != 0000011 ORN, ORNS (register) ORNS, shift or rotate by value 01x1 UNALLOCATED 0100 0 0000011 EOR, EORS (register) EOR, rotate right with extend 0100 0 != 0000011 EOR, EORS (register) EOR, shift or rotate by value 0100 1 0000011 1111 TEQ (register) Rotate right with extend 0100 1 0000011 != 1111 EOR, EORS (register) EORS, rotate right with extend 0100 1 != 0000011 1111 TEQ (register) Shift or rotate by value 0100 1 != 0000011 != 1111 EOR, EORS (register) EORS, shift or rotate by value 0110 0 xxxxxx1 UNALLOCATED 0110 0 xxxxx00 PKHBT, PKHTB PKHBT 0110 0 xxxxx10 PKHBT, PKHTB PKHTB 0110 1 UNALLOCATED 1000 0 1101 0000011 ADD, ADDS (SP plus register) ADD, rotate right with extend 1000 0 1101 != 0000011 ADD, ADDS (SP plus register) ADD, shift or rotate by value 1000 0 != 1101 0000011 ADD, ADDS (register) ADD, rotate right with extend 1000 0 != 1101 != 0000011 ADD, ADDS (register) ADD, shift or rotate by value 1000 1 0000011 1111 CMN (register) Rotate right with extend 1000 1 != 0000011 1111 CMN (register) Shift or rotate by value 1000 1 1101 0000011 != 1111 ADD, ADDS (SP plus register) ADDS, rotate right with extend 1000 1 1101 != 0000011 != 1111 ADD, ADDS (SP plus register) ADDS, shift or rotate by value 1000 1 != 1101 0000011 != 1111 ADD, ADDS (register) ADDS, rotate right with extend 1000 1 != 1101 != 0000011 != 1111 ADD, ADDS (register) ADDS, shift or rotate by value 1001 UNALLOCATED 1010 0 0000011 ADC, ADCS (register) ADC, rotate right with extend 1010 0 != 0000011 ADC, ADCS (register) ADC, shift or rotate by value 1010 1 0000011 ADC, ADCS (register) ADCS, rotate right with extend 1010 1 != 0000011 ADC, ADCS (register) ADCS, shift or rotate by value 1011 0 0000011 SBC, SBCS (register) SBC, rotate right with extend 1011 0 != 0000011 SBC, SBCS (register) SBC, shift or rotate by value 1011 1 0000011 SBC, SBCS (register) SBCS, rotate right with extend 1011 1 != 0000011 SBC, SBCS (register) SBCS, shift or rotate by value 1100 UNALLOCATED 1101 0 1101 0000011 SUB, SUBS (SP minus register) SUB, rotate right with extend 1101 0 1101 != 0000011 SUB, SUBS (SP minus register) SUB, shift or rotate by value 1101 0 != 1101 0000011 SUB, SUBS (register) SUB, rotate right with extend 1101 0 != 1101 != 0000011 SUB, SUBS (register) SUB, shift or rotate by value 1101 1 0000011 1111 CMP (register) Rotate right with extend 1101 1 != 0000011 1111 CMP (register) Shift or rotate by value 1101 1 1101 0000011 != 1111 SUB, SUBS (SP minus register) SUBS, rotate right with extend 1101 1 1101 != 0000011 != 1111 SUB, SUBS (SP minus register) SUBS, shift or rotate by value 1101 1 != 1101 0000011 != 1111 SUB, SUBS (register) SUBS, rotate right with extend 1101 1 != 1101 != 0000011 != 1111 SUB, SUBS (register) SUBS, shift or rotate by value 1110 0 0000011 RSB, RSBS (register) RSB, rotate right with extend 1110 0 != 0000011 RSB, RSBS (register) RSB, shift or rotate by value 1110 1 0000011 RSB, RSBS (register) RSBS, rotate right with extend 1110 1 != 0000011 RSB, RSBS (register) RSBS, shift or rotate by value 1111 UNALLOCATED 1 1 1 0 1 0 0 0 0 1 0 Decode fields Instruction page Encoding L 0 STREX T1 1 LDREX T1 1 1 1 0 1 0 0 0 1 1 0 1 (1) (1) (1) (1) (0) (0) (0) (0) 0 0 0 Decode fields Instruction page Encoding H 0 TBB, TBH Byte 1 TBB, TBH Halfword 1 1 1 0 1 0 0 0 1 1 0 0 1 Decode fields Instruction page Encoding L sz 10 UNALLOCATED 0 00 STREXB T1 0 01 STREXH T1 0 11 STREXD T1 1 00 LDREXB T1 1 01 LDREXH T1 1 11 LDREXD T1 1 1 1 0 1 0 0 0 1 1 0 1 Decode fields Instruction page Encoding L op sz 0 11 UNALLOCATED 0 0 00 STLB T1 0 0 01 STLH T1 0 0 10 STL T1 0 1 00 STLEXB T1 0 1 01 STLEXH T1 0 1 10 STLEX T1 0 1 11 STLEXD T1 1 0 00 LDAB T1 1 0 01 LDAH T1 1 0 10 LDA T1 1 1 00 LDAEXB T1 1 1 01 LDAEXH T1 1 1 10 LDAEX T1 1 1 11 LDAEXD T1 1 1 1 0 1 0 0 0 1 1 != 1111 Decode fields Instruction page Encoding L 0 STRD (immediate) Post-indexed 1 LDRD (immediate) Post-indexed 1 1 1 0 1 0 0 1 1 0 != 1111 Decode fields Instruction page Encoding L 0 STRD (immediate) Offset 1 LDRD (immediate) Offset 1 1 1 0 1 0 0 1 1 1 != 1111 Decode fields Instruction page Encoding L 0 STRD (immediate) Pre-indexed 1 LDRD (immediate) Pre-indexed 1 1 1 0 1 0 0 1 1 1 1 1 Decode fields Instruction page Encoding L 0 UNALLOCATED 1 LDRD (literal) T1 1 1 1 0 1 0 0 0 Decode fields Instruction page Encoding opc L 00 0 SRS, SRSDA, SRSDB, SRSIA, SRSIB T1 00 1 RFE, RFEDA, RFEDB, RFEIA, RFEIB T1 01 0 STM, STMIA, STMEA T2 01 1 LDM, LDMIA, LDMFD T2 10 0 STMDB, STMFD T1 10 1 LDMDB, LDMEA T1 11 0 SRS, SRSDA, SRSDB, SRSIA, SRSIB T2 11 1 RFE, RFEDA, RFEDB, RFEIA, RFEIB T2 1 1 1 1 1 0 0 0 0 != 1111 0 0 0 0 0 0 Decode fields Instruction page Encoding size L Rt 00 0 STRB (register) T2 00 1 1111 PLD, PLDW (register) Preload read 00 1 != 1111 LDRB (register) T2 01 0 STRH (register) T2 01 1 1111 PLD, PLDW (register) Preload write 01 1 != 1111 LDRH (register) T2 10 0 STR (register) T2 10 1 LDR (register) T2 11 UNALLOCATED 1 1 1 1 1 0 0 0 0 != 1111 1 0 1 Decode fields Instruction page Encoding size L 00 0 STRB (immediate) Post-indexed 00 1 LDRB (immediate) Post-indexed 01 0 STRH (immediate) Post-indexed 01 1 LDRH (immediate) Post-indexed 10 0 STR (immediate) Post-indexed 10 1 LDR (immediate) Post-indexed 11 UNALLOCATED 1 1 1 1 1 0 0 0 0 != 1111 1 1 0 0 Decode fields Instruction page Encoding size L Rt 00 0 STRB (immediate) Offset 00 1 1111 PLD, PLDW (immediate) Preload read 00 1 != 1111 LDRB (immediate) Offset 01 0 STRH (immediate) Offset 01 1 1111 PLD, PLDW (immediate) Preload write 01 1 != 1111 LDRH (immediate) Offset 10 0 STR (immediate) Offset 10 1 LDR (immediate) Offset 11 UNALLOCATED 1 1 1 1 1 0 0 0 0 != 1111 1 1 1 0 Decode fields Instruction page Encoding size L 00 0 STRBT T1 00 1 LDRBT T1 01 0 STRHT T1 01 1 LDRHT T1 10 0 STRT T1 10 1 LDRT T1 11 UNALLOCATED 1 1 1 1 1 0 0 0 0 != 1111 1 1 1 Decode fields Instruction page Encoding size L 00 0 STRB (immediate) Pre-indexed 00 1 LDRB (immediate) Pre-indexed 01 0 STRH (immediate) Pre-indexed 01 1 LDRH (immediate) Pre-indexed 10 0 STR (immediate) Pre-indexed 10 1 LDR (immediate) Pre-indexed 11 UNALLOCATED 1 1 1 1 1 0 0 0 1 != 1111 Decode fields Instruction page Encoding size L Rt 00 0 STRB (immediate) T2 00 1 1111 PLD, PLDW (immediate) Preload read 00 1 != 1111 LDRB (immediate) T2 01 0 STRH (immediate) T2 01 1 1111 PLD, PLDW (immediate) Preload write 01 1 != 1111 LDRH (immediate) T2 10 0 STR (immediate) T3 10 1 LDR (immediate) T3 11 UNALLOCATED 1 1 1 1 1 0 0 0 1 1 1 1 Decode fields Instruction page Encoding size L Rt 0 UNALLOCATED 0x 1 1111 PLD (literal) T1 00 1 != 1111 LDRB (literal) T1 01 1 != 1111 LDRH (literal) T1 10 1 LDR (literal) T2 11 1 UNALLOCATED 1 1 1 1 1 0 0 1 0 1 != 1111 0 0 0 0 0 0 Decode fields Instruction page Encoding size Rt 00 1111 PLI (register) T1 00 != 1111 LDRSB (register) T2 01 1111 Reserved hint, behaves as NOP 01 != 1111 LDRSH (register) T2 1x UNALLOCATED 1 1 1 1 1 0 0 1 0 1 != 1111 1 0 1 Decode fields Instruction page Encoding size 00 LDRSB (immediate) Post-indexed 01 LDRSH (immediate) Post-indexed 1x UNALLOCATED 1 1 1 1 1 0 0 1 0 1 != 1111 1 1 0 0 Decode fields Instruction page Encoding size Rt 00 1111 PLI (immediate, literal) T2 00 != 1111 LDRSB (immediate) Offset 01 1111 Reserved hint, behaves as NOP 01 != 1111 LDRSH (immediate) Offset 1x UNALLOCATED 1 1 1 1 1 0 0 1 0 1 != 1111 1 1 1 0 Decode fields Instruction page Encoding size 00 LDRSBT T1 01 LDRSHT T1 1x UNALLOCATED 1 1 1 1 1 0 0 1 0 1 != 1111 1 1 1 Decode fields Instruction page Encoding size 00 LDRSB (immediate) Pre-indexed 01 LDRSH (immediate) Pre-indexed 1x UNALLOCATED 1 1 1 1 1 0 0 1 1 1 != 1111 Decode fields Instruction page Encoding size Rt 00 1111 PLI (immediate, literal) T1 00 != 1111 LDRSB (immediate) T1 01 1111 Reserved hint, behaves as NOP 01 != 1111 LDRSH (immediate) T1 1x UNALLOCATED 1 1 1 1 1 0 0 1 1 1 1 1 1 Decode fields Instruction page Encoding size Rt 00 1111 PLI (immediate, literal) T3 00 != 1111 LDRSB (literal) T1 01 1111 Reserved hint, behaves as NOP 01 != 1111 LDRSH (literal) T1 1x UNALLOCATED 1 1 1 1 1 0 1 1 1 != 0x1 Decode fields Instruction page Encoding op1 op2 xx0 00x1 UNALLOCATED xx0 0010 UNALLOCATED 0x0 != 00xx UNALLOCATED 000 0000 SMULL, SMULLS T1 010 0000 UMULL, UMULLS T1 1xx 0100 UNALLOCATED 1x0 01x1 UNALLOCATED 1x1 00xx UNALLOCATED 1x1 0101 UNALLOCATED 1x1 011x UNALLOCATED 100 x110 UNALLOCATED 100 0000 SMLAL, SMLALS T1 100 1000 SMLALBB, SMLALBT, SMLALTB, SMLALTT SMLALBB 100 1001 SMLALBB, SMLALBT, SMLALTB, SMLALTT SMLALBT 100 1010 SMLALBB, SMLALBT, SMLALTB, SMLALTT SMLALTB 100 1011 SMLALBB, SMLALBT, SMLALTB, SMLALTT SMLALTT 100 1100 SMLALD, SMLALDX SMLALD 100 1101 SMLALD, SMLALDX SMLALDX 100 1111 UNALLOCATED 101 10xx UNALLOCATED 101 1100 SMLSLD, SMLSLDX SMLSLD 101 1101 SMLSLD, SMLSLDX SMLSLDX 101 111x UNALLOCATED 11x 1xxx UNALLOCATED 110 0000 UMLAL, UMLALS T1 110 0110 UMAAL T1 1 1 1 1 1 0 1 1 1 0 x 1 Decode fields Instruction page Encoding op1 op2 0x1 != 1111 UNALLOCATED 001 1111 SDIV T1 011 1111 UDIV T1 1 1 1 1 1 0 1 1 0 0 0 Decode fields Instruction page Encoding op1 Ra op2 000 01 MLS T1 000 1111 00 MUL, MULS T2 000 != 1111 00 MLA, MLAS T1 001 1111 00 SMULBB, SMULBT, SMULTB, SMULTT SMULBB 001 1111 01 SMULBB, SMULBT, SMULTB, SMULTT SMULBT 001 1111 10 SMULBB, SMULBT, SMULTB, SMULTT SMULTB 001 1111 11 SMULBB, SMULBT, SMULTB, SMULTT SMULTT 001 != 1111 00 SMLABB, SMLABT, SMLATB, SMLATT SMLABB 001 != 1111 01 SMLABB, SMLABT, SMLATB, SMLATT SMLABT 001 != 1111 10 SMLABB, SMLABT, SMLATB, SMLATT SMLATB 001 != 1111 11 SMLABB, SMLABT, SMLATB, SMLATT SMLATT 010 1111 00 SMUAD, SMUADX SMUAD 010 1111 01 SMUAD, SMUADX SMUADX 010 != 1111 00 SMLAD, SMLADX SMLAD 010 != 1111 01 SMLAD, SMLADX SMLADX 011 1111 00 SMULWB, SMULWT SMULWB 011 1111 01 SMULWB, SMULWT SMULWT 011 != 1111 00 SMLAWB, SMLAWT SMLAWB 011 != 1111 01 SMLAWB, SMLAWT SMLAWT 100 1111 00 SMUSD, SMUSDX SMUSD 100 1111 01 SMUSD, SMUSDX SMUSDX 100 != 1111 00 SMLSD, SMLSDX SMLSD 100 != 1111 01 SMLSD, SMLSDX SMLSDX 101 1111 00 SMMUL, SMMULR SMMUL 101 1111 01 SMMUL, SMMULR SMMULR 101 != 1111 00 SMMLA, SMMLAR SMMLA 101 != 1111 01 SMMLA, SMMLAR SMMLAR 110 00 SMMLS, SMMLSR SMMLS 110 01 SMMLS, SMMLSR SMMLSR 111 01 UNALLOCATED 111 1111 00 USAD8 T1 111 != 1111 00 USADA8 T1 != 001 1x UNALLOCATED 1 1 1 1 1 1 1 0 Decode fields Instruction page Encoding U size opc Q o1 0000 0 0 VHADD 64-bit SIMD vector 0000 0 1 VQADD 64-bit SIMD vector 0000 1 0 VHADD 128-bit SIMD vector 0000 1 1 VQADD 128-bit SIMD vector 0001 0 0 VRHADD 64-bit SIMD vector 0001 1 0 VRHADD 128-bit SIMD vector 0010 0 0 VHSUB 64-bit SIMD vector 0010 0 1 VQSUB 64-bit SIMD vector 0010 1 0 VHSUB 128-bit SIMD vector 0010 1 1 VQSUB 128-bit SIMD vector 0011 0 0 VCGT (register) 64-bit SIMD vector 0011 0 1 VCGE (register) 64-bit SIMD vector 0011 1 0 VCGT (register) 128-bit SIMD vector 0011 1 1 VCGE (register) 128-bit SIMD vector 0100 0 0 VSHL (register) 64-bit SIMD vector 0100 0 1 VQSHL (register) 64-bit SIMD vector 0100 1 0 VSHL (register) 128-bit SIMD vector 0100 1 1 VQSHL (register) 128-bit SIMD vector 0101 0 0 VRSHL 64-bit SIMD vector 0101 0 1 VQRSHL 64-bit SIMD vector 0101 1 0 VRSHL 128-bit SIMD vector 0101 1 1 VQRSHL 128-bit SIMD vector 0110 0 0 VMAX (integer) 64-bit SIMD vector 0110 0 1 VMIN (integer) 64-bit SIMD vector 0110 1 0 VMAX (integer) 128-bit SIMD vector 0110 1 1 VMIN (integer) 128-bit SIMD vector 0111 0 0 VABD (integer) 64-bit SIMD vector 0111 0 1 VABA 64-bit SIMD vector 0111 1 0 VABD (integer) 128-bit SIMD vector 0111 1 1 VABA 128-bit SIMD vector 1001 0 1 VMUL (integer and polynomial) 64-bit SIMD vector 1001 1 1 VMUL (integer and polynomial) 128-bit SIMD vector 1010 0 0 VPMAX (integer) T1 1010 0 1 VPMIN (integer) T1 1010 1 UNALLOCATED 0 1000 0 0 VADD (integer) 64-bit SIMD vector 0 1000 0 1 VTST 64-bit SIMD vector 0 1000 1 0 VADD (integer) 128-bit SIMD vector 0 1000 1 1 VTST 128-bit SIMD vector 0 1001 0 0 VMLA (integer) 64-bit SIMD vector 0 1001 1 0 VMLA (integer) 128-bit SIMD vector 0 1011 1 VPADD (integer) T1 0 1011 0 0 VQDMULH 64-bit SIMD vector 0 1011 1 0 VQDMULH 128-bit SIMD vector 0 0x 1100 0 1 VFMA 64-bit SIMD vector 0 0x 1100 1 1 VFMA 128-bit SIMD vector 0 0x 1101 0 0 VADD (floating-point) 64-bit SIMD vector 0 0x 1101 0 1 VMLA (floating-point) 64-bit SIMD vector 0 0x 1101 1 0 VADD (floating-point) 128-bit SIMD vector 0 0x 1101 1 1 VMLA (floating-point) 128-bit SIMD vector 0 0x 1110 1 UNALLOCATED 0 0x 1110 0 0 VCEQ (register) 64-bit SIMD vector 0 0x 1110 1 0 VCEQ (register) 128-bit SIMD vector 0 0x 1111 0 0 VMAX (floating-point) 64-bit SIMD vector 0 0x 1111 0 1 VRECPS 64-bit SIMD vector 0 0x 1111 1 0 VMAX (floating-point) 128-bit SIMD vector 0 0x 1111 1 1 VRECPS 128-bit SIMD vector 0 00 0001 0 1 VAND (register) 64-bit SIMD vector 0 00 0001 1 1 VAND (register) 128-bit SIMD vector 0 00 1100 0 SHA1C T1 0 01 0001 0 1 VBIC (register) 64-bit SIMD vector 0 01 0001 1 1 VBIC (register) 128-bit SIMD vector 0 01 1100 0 SHA1P T1 0 1x 1100 0 1 VFMS 64-bit SIMD vector 0 1x 1100 1 1 VFMS 128-bit SIMD vector 0 1x 1101 0 0 VSUB (floating-point) 64-bit SIMD vector 0 1x 1101 0 1 VMLS (floating-point) 64-bit SIMD vector 0 1x 1101 1 0 VSUB (floating-point) 128-bit SIMD vector 0 1x 1101 1 1 VMLS (floating-point) 128-bit SIMD vector 0 1x 1110 UNALLOCATED 0 1x 1111 0 0 VMIN (floating-point) 64-bit SIMD vector 0 1x 1111 0 1 VRSQRTS 64-bit SIMD vector 0 1x 1111 1 0 VMIN (floating-point) 128-bit SIMD vector 0 1x 1111 1 1 VRSQRTS 128-bit SIMD vector 0 10 0001 0 1 VORR (register) 64-bit SIMD vector 0 10 0001 1 1 VORR (register) 128-bit SIMD vector 0 10 1100 0 SHA1M T1 0 11 0001 0 1 VORN (register) 64-bit SIMD vector 0 11 0001 1 1 VORN (register) 128-bit SIMD vector 0 11 1100 0 SHA1SU0 T1 1 1000 0 0 VSUB (integer) 64-bit SIMD vector 1 1000 0 1 VCEQ (register) 64-bit SIMD vector 1 1000 1 0 VSUB (integer) 128-bit SIMD vector 1 1000 1 1 VCEQ (register) 128-bit SIMD vector 1 1001 0 0 VMLS (integer) 64-bit SIMD vector 1 1001 1 0 VMLS (integer) 128-bit SIMD vector 1 1011 0 0 VQRDMULH 64-bit SIMD vector 1 1011 0 1 VQRDMLAH 64-bit SIMD vector 1 1011 1 0 VQRDMULH 128-bit SIMD vector 1 1011 1 1 VQRDMLAH 128-bit SIMD vector 1 1100 0 1 VQRDMLSH 64-bit SIMD vector 1 1100 1 1 VQRDMLSH 128-bit SIMD vector 1 1111 1 0 UNALLOCATED 1 0x 1101 0 VPADD (floating-point) T1 1 0x 1101 0 1 VMUL (floating-point) 64-bit SIMD vector 1 0x 1101 1 1 VMUL (floating-point) 128-bit SIMD vector 1 0x 1110 0 0 VCGE (register) 64-bit SIMD vector 1 0x 1110 0 1 VACGE 64-bit SIMD vector 1 0x 1110 1 0 VCGE (register) 128-bit SIMD vector 1 0x 1110 1 1 VACGE 128-bit SIMD vector 1 0x 1111 0 0 VPMAX (floating-point) T1 1 0x 1111 0 1 VMAXNM 64-bit SIMD vector 1 0x 1111 1 1 VMAXNM 128-bit SIMD vector 1 00 0001 0 1 VEOR 64-bit SIMD vector 1 00 0001 1 1 VEOR 128-bit SIMD vector 1 00 1100 0 SHA256H T1 1 01 0001 0 1 VBSL 64-bit SIMD vector 1 01 0001 1 1 VBSL 128-bit SIMD vector 1 01 1100 0 SHA256H2 T1 1 1x 1101 1 UNALLOCATED 1 1x 1101 0 0 VABD (floating-point) 64-bit SIMD vector 1 1x 1101 1 0 VABD (floating-point) 128-bit SIMD vector 1 1x 1110 0 0 VCGT (register) 64-bit SIMD vector 1 1x 1110 0 1 VACGT 64-bit SIMD vector 1 1x 1110 1 0 VCGT (register) 128-bit SIMD vector 1 1x 1110 1 1 VACGT 128-bit SIMD vector 1 1x 1111 0 0 VPMIN (floating-point) T1 1 1x 1111 0 1 VMINNM 64-bit SIMD vector 1 1x 1111 1 1 VMINNM 128-bit SIMD vector 1 10 0001 0 1 VBIT 64-bit SIMD vector 1 10 0001 1 1 VBIT 128-bit SIMD vector 1 10 1100 0 SHA256SU1 T1 1 11 0001 0 1 VBIF 64-bit SIMD vector 1 11 0001 1 1 VBIF 128-bit SIMD vector 1 11 1100 0 UNALLOCATED 1 1 1 0 1 1 1 1 1 1 1 0 Decode fields Instruction page Encoding Q 0 VEXT (byte elements) 64-bit SIMD vector 1 VEXT (byte elements) 128-bit SIMD vector 1 1 1 1 1 1 1 1 1 1 1 0 0 Decode fields Instruction page Encoding size opc1 opc2 Q 00 0000 0 VREV64 64-bit SIMD vector 00 0000 1 VREV64 128-bit SIMD vector 00 0001 0 VREV32 64-bit SIMD vector 00 0001 1 VREV32 128-bit SIMD vector 00 0010 0 VREV16 64-bit SIMD vector 00 0010 1 VREV16 128-bit SIMD vector 00 0011 UNALLOCATED 00 010x 0 VPADDL 64-bit SIMD vector 00 010x 1 VPADDL 128-bit SIMD vector 00 0110 0 AESE T1 00 0110 1 AESD T1 00 0111 0 AESMC T1 00 0111 1 AESIMC T1 00 1000 0 VCLS 64-bit SIMD vector 00 1000 1 VCLS 128-bit SIMD vector 00 1001 0 VCLZ 64-bit SIMD vector 00 1001 1 VCLZ 128-bit SIMD vector 00 1010 0 VCNT 64-bit SIMD vector 00 1010 1 VCNT 128-bit SIMD vector 00 1011 0 VMVN (register) 64-bit SIMD vector 00 1011 1 VMVN (register) 128-bit SIMD vector 00 110x 0 VPADAL 64-bit SIMD vector 00 110x 1 VPADAL 128-bit SIMD vector 00 1110 0 VQABS 64-bit SIMD vector 00 1110 1 VQABS 128-bit SIMD vector 00 1111 0 VQNEG 64-bit SIMD vector 00 1111 1 VQNEG 128-bit SIMD vector 01 x000 0 VCGT (immediate #0) 64-bit SIMD vector 01 x000 1 VCGT (immediate #0) 128-bit SIMD vector 01 x001 0 VCGE (immediate #0) 64-bit SIMD vector 01 x001 1 VCGE (immediate #0) 128-bit SIMD vector 01 x010 0 VCEQ (immediate #0) 64-bit SIMD vector 01 x010 1 VCEQ (immediate #0) 128-bit SIMD vector 01 x011 0 VCLE (immediate #0) 64-bit SIMD vector 01 x011 1 VCLE (immediate #0) 128-bit SIMD vector 01 x100 0 VCLT (immediate #0) 64-bit SIMD vector 01 x100 1 VCLT (immediate #0) 128-bit SIMD vector 01 x110 0 VABS 64-bit SIMD vector 01 x110 1 VABS 128-bit SIMD vector 01 x111 0 VNEG 64-bit SIMD vector 01 x111 1 VNEG 128-bit SIMD vector 01 0101 0 UNALLOCATED 01 0101 1 SHA1H T1 01 1101 UNALLOCATED 10 x110 1 UNALLOCATED 10 0001 0 VTRN 64-bit SIMD vector 10 0001 1 VTRN 128-bit SIMD vector 10 0010 0 VUZP 64-bit SIMD vector 10 0010 1 VUZP 128-bit SIMD vector 10 0011 0 VZIP 64-bit SIMD vector 10 0011 1 VZIP 128-bit SIMD vector 10 0100 0 VMOVN T1 10 0100 1 VQMOVN, VQMOVUN Unsigned result 10 0101 VQMOVN, VQMOVUN Signed result 10 0110 0 VSHLL T2 10 0111 0 SHA1SU1 T1 10 0111 1 SHA256SU0 T1 10 1000 0 VRINTN (Advanced SIMD) 64-bit SIMD vector 10 1000 1 VRINTN (Advanced SIMD) 128-bit SIMD vector 10 1001 0 VRINTX (Advanced SIMD) 64-bit SIMD vector 10 1001 1 VRINTX (Advanced SIMD) 128-bit SIMD vector 10 1010 0 VRINTA (Advanced SIMD) 64-bit SIMD vector 10 1010 1 VRINTA (Advanced SIMD) 128-bit SIMD vector 10 1011 0 VRINTZ (Advanced SIMD) 64-bit SIMD vector 10 1011 1 VRINTZ (Advanced SIMD) 128-bit SIMD vector 10 1100 0 VCVT (between half-precision and single-precision, Advanced SIMD) Single-precision to half-precision 10 1101 0 VRINTM (Advanced SIMD) 64-bit SIMD vector 10 1101 1 VRINTM (Advanced SIMD) 128-bit SIMD vector 10 1110 0 VCVT (between half-precision and single-precision, Advanced SIMD) Half-precision to single-precision 10 1111 0 VRINTP (Advanced SIMD) 64-bit SIMD vector 10 1111 1 VRINTP (Advanced SIMD) 128-bit SIMD vector 11 000x 0 VCVTA (Advanced SIMD) 64-bit SIMD vector 11 000x 1 VCVTA (Advanced SIMD) 128-bit SIMD vector 11 001x 0 VCVTN (Advanced SIMD) 64-bit SIMD vector 11 001x 1 VCVTN (Advanced SIMD) 128-bit SIMD vector 11 010x 0 VCVTP (Advanced SIMD) 64-bit SIMD vector 11 010x 1 VCVTP (Advanced SIMD) 128-bit SIMD vector 11 011x 0 VCVTM (Advanced SIMD) 64-bit SIMD vector 11 011x 1 VCVTM (Advanced SIMD) 128-bit SIMD vector 11 10x0 0 VRECPE 64-bit SIMD vector 11 10x0 1 VRECPE 128-bit SIMD vector 11 10x1 0 VRSQRTE 64-bit SIMD vector 11 10x1 1 VRSQRTE 128-bit SIMD vector 11 11xx 0 VCVT (between floating-point and integer, Advanced SIMD) 64-bit SIMD vector 11 11xx 1 VCVT (between floating-point and integer, Advanced SIMD) 128-bit SIMD vector 00 10 0000 0 VSWP 64-bit SIMD vector 00 10 0000 1 VSWP 128-bit SIMD vector 01 10 1100 1 VCVT (from single-precision to BFloat16, Advanced SIMD) T1 != 00 10 0000 UNALLOCATED != 01 10 1100 1 UNALLOCATED 1 1 1 1 1 1 1 1 1 1 1 1 0 0 Decode fields Instruction page Encoding op 0 VTBL, VTBX VTBL 1 VTBL, VTBX VTBX 1 1 1 1 1 1 1 1 1 1 1 1 1 0 Decode fields Instruction page Encoding opc Q 000 0 VDUP (scalar) 000 1 VDUP (scalar) != 000 UNALLOCATED 1 1 1 1 1 1 1 1 != 11 0 0 Decode fields Instruction page Encoding U opc 0000 VADDL T1 0001 VADDW T1 0010 VSUBL T1 0011 VSUBW T1 0101 VABAL T1 0111 VABDL (integer) T1 1000 VMLAL (integer) T1 1010 VMLSL (integer) T1 11x0 VMULL (integer and polynomial) T1 0 0100 VADDHN T1 0 0110 VSUBHN T1 0 1001 VQDMLAL T1 0 1011 VQDMLSL T1 0 1101 VQDMULL T1 0 1111 UNALLOCATED 1 0100 VRADDHN T1 1 0110 VRSUBHN T1 1 1xx1 UNALLOCATED 1 1 1 1 1 1 1 1 != 11 1 0 Decode fields Instruction page Encoding Q opc 0010 VMLAL (by scalar) T1 0110 VMLSL (by scalar) T1 1010 VMULL (by scalar) T1 0 000x VMLA (by scalar) 64-bit SIMD vector 0 0011 VQDMLAL T2 0 010x VMLS (by scalar) 64-bit SIMD vector 0 0111 VQDMLSL T2 0 100x VMUL (by scalar) 64-bit SIMD vector 0 1011 VQDMULL T2 0 1100 VQDMULH 64-bit SIMD vector 0 1101 VQRDMULH 64-bit SIMD vector 0 1110 VQRDMLAH 64-bit SIMD vector 0 1111 VQRDMLSH 64-bit SIMD vector 1 0x11 UNALLOCATED 1 000x VMLA (by scalar) 128-bit SIMD vector 1 010x VMLS (by scalar) 128-bit SIMD vector 1 100x VMUL (by scalar) 128-bit SIMD vector 1 1011 UNALLOCATED 1 1100 VQDMULH 128-bit SIMD vector 1 1101 VQRDMULH 128-bit SIMD vector 1 1110 VQRDMLAH 128-bit SIMD vector 1 1111 VQRDMLSH 128-bit SIMD vector 1 1 1 1 1 1 1 1 0 0 0 0 1 Decode fields Instruction page Encoding cmode Q op 0xx0 0 0 VMOV (immediate) 64-bit SIMD vector 0xx0 0 1 VMVN (immediate) 64-bit SIMD vector 0xx0 1 0 VMOV (immediate) 128-bit SIMD vector 0xx0 1 1 VMVN (immediate) 128-bit SIMD vector 0xx1 0 0 VORR (immediate) 64-bit SIMD vector 0xx1 0 1 VBIC (immediate) 64-bit SIMD vector 0xx1 1 0 VORR (immediate) 128-bit SIMD vector 0xx1 1 1 VBIC (immediate) 128-bit SIMD vector 10x0 0 0 VMOV (immediate) 64-bit SIMD vector 10x0 0 1 VMVN (immediate) 64-bit SIMD vector 10x0 1 0 VMOV (immediate) 128-bit SIMD vector 10x0 1 1 VMVN (immediate) 128-bit SIMD vector 10x1 0 0 VORR (immediate) 64-bit SIMD vector 10x1 0 1 VBIC (immediate) 64-bit SIMD vector 10x1 1 0 VORR (immediate) 128-bit SIMD vector 10x1 1 1 VBIC (immediate) 128-bit SIMD vector 11xx 0 0 VMOV (immediate) 64-bit SIMD vector 11xx 1 0 VMOV (immediate) 128-bit SIMD vector 110x 0 1 VMVN (immediate) 64-bit SIMD vector 110x 1 1 VMVN (immediate) 128-bit SIMD vector 1110 0 1 VMOV (immediate) 64-bit SIMD vector 1110 1 1 VMOV (immediate) 128-bit SIMD vector 1111 1 UNALLOCATED 1 1 1 1 1 1 1 1 1 Decode fields Instruction page Encoding U imm3H imm3L opc L Q 1xxx 1 UNALLOCATED 000 0000 1 0 VSHR 64-bit SIMD vector 000 0000 1 1 VSHR 128-bit SIMD vector 000 0001 1 0 VSRA 64-bit SIMD vector 000 0001 1 1 VSRA 128-bit SIMD vector 000 0010 1 0 VRSHR 64-bit SIMD vector 000 0010 1 1 VRSHR 128-bit SIMD vector 000 0011 1 0 VRSRA 64-bit SIMD vector 000 0011 1 1 VRSRA 128-bit SIMD vector 000 0111 1 0 VQSHL, VQSHLU (immediate) 64-bit SIMD vector, signed result 000 0111 1 1 VQSHL, VQSHLU (immediate) 128-bit SIMD vector, signed result 001 000 1010 0 0 VMOVL T1 001 != 000 1010 0 0 VSHLL T1 010 000 1010 0 0 VMOVL T1 010 != 000 1010 0 0 VSHLL T1 011 1010 0 0 VSHLL T1 100 000 1010 0 0 VMOVL T1 100 != 000 1010 0 0 VSHLL T1 101 1010 0 0 VSHLL T1 11x 1010 0 0 VSHLL T1 != 000 0000 0 VSHR 64-bit SIMD vector != 000 0000 1 VSHR 128-bit SIMD vector != 000 0001 0 VSRA 64-bit SIMD vector != 000 0001 1 VSRA 128-bit SIMD vector != 000 0010 0 VRSHR 64-bit SIMD vector != 000 0010 1 VRSHR 128-bit SIMD vector != 000 0011 0 VRSRA 64-bit SIMD vector != 000 0011 1 VRSRA 128-bit SIMD vector != 000 0111 0 VQSHL, VQSHLU (immediate) 64-bit SIMD vector, signed result != 000 0111 1 VQSHL, VQSHLU (immediate) 128-bit SIMD vector, signed result != 000 1001 0 0 VQSHRN, VQSHRUN Signed result != 000 1001 0 1 VQRSHRN, VQRSHRUN Signed result != 000 1010 0 1 UNALLOCATED != 000 1011 0 UNALLOCATED != 000 11xx 0 0 VCVT (between floating-point and fixed-point, Advanced SIMD) 64-bit SIMD vector != 000 11xx 0 1 VCVT (between floating-point and fixed-point, Advanced SIMD) 128-bit SIMD vector 0 01x0 1 UNALLOCATED 0 000 0101 1 0 VSHL (immediate) 64-bit SIMD vector 0 000 0101 1 1 VSHL (immediate) 128-bit SIMD vector 0 != 000 01x0 0 UNALLOCATED 0 != 000 0101 0 VSHL (immediate) 64-bit SIMD vector 0 != 000 0101 1 VSHL (immediate) 128-bit SIMD vector 0 != 000 1000 0 0 VSHRN T1 0 != 000 1000 0 1 VRSHRN T1 1 000 0100 1 0 VSRI 64-bit SIMD vector 1 000 0100 1 1 VSRI 128-bit SIMD vector 1 000 0101 1 0 VSLI 64-bit SIMD vector 1 000 0101 1 1 VSLI 128-bit SIMD vector 1 000 0110 1 0 VQSHL, VQSHLU (immediate) 64-bit SIMD vector, unsigned result 1 000 0110 1 1 VQSHL, VQSHLU (immediate) 128-bit SIMD vector, unsigned result 1 != 000 0100 0 VSRI 64-bit SIMD vector 1 != 000 0100 1 VSRI 128-bit SIMD vector 1 != 000 0101 0 VSLI 64-bit SIMD vector 1 != 000 0101 1 VSLI 128-bit SIMD vector 1 != 000 0110 0 VQSHL, VQSHLU (immediate) 64-bit SIMD vector, unsigned result 1 != 000 0110 1 VQSHL, VQSHLU (immediate) 128-bit SIMD vector, unsigned result 1 != 000 1000 0 0 VQSHRN, VQSHRUN Unsigned result 1 != 000 1000 0 1 VQRSHRN, VQRSHRUN Unsigned result 1 1 1 0 1 1 0 0 0 0 1 0 Decode fields Instruction page Encoding D op size opc2 o3 0 UNALLOCATED 1 0x UNALLOCATED 1 1x 00 0 UNALLOCATED 1 1x != 00 UNALLOCATED 1 0 10 00 1 VMOV (between two general-purpose registers and two single-precision registers) From general-purpose registers 1 0 11 00 1 VMOV (between two general-purpose registers and a doubleword floating-point register) From general-purpose registers 1 1 10 00 1 VMOV (between two general-purpose registers and two single-precision registers) To general-purpose registers 1 1 11 00 1 VMOV (between two general-purpose registers and a doubleword floating-point register) To general-purpose registers 1 1 1 0 1 1 0 0 0 0 1 1 1 Decode fields Instruction page Encoding D L 0 UNALLOCATED 1 0 MCRR T1 1 1 MRRC T1 1 1 1 0 1 1 0 1 0 Decode fields Instruction page Encoding P U W L Rn size imm8 1 0x UNALLOCATED 0 0 1 1x UNALLOCATED 0 1 0 10 VSTM, VSTMDB, VSTMIA Increment After 0 1 0 11 xxxxxxx0 VSTM, VSTMDB, VSTMIA Increment After 0 1 0 11 xxxxxxx1 FSTMDBX, FSTMIAX Increment After 0 1 1 10 VLDM, VLDMDB, VLDMIA Increment After 0 1 1 11 xxxxxxx0 VLDM, VLDMDB, VLDMIA Increment After 0 1 1 11 xxxxxxx1 FLDM*X (FLDMDBX, FLDMIAX) Increment After 0 1 0 0x UNALLOCATED 1 0 00 UNALLOCATED 1 0 0 01 VSTR Half-precision scalar 1 0 0 10 VSTR Single-precision scalar 1 0 0 11 VSTR Double-precision scalar 1 0 1 1111 01 VLDR (literal) Half-precision scalar 1 0 1 1111 10 VLDR (literal) Single-precision scalar 1 0 1 1111 11 VLDR (literal) Double-precision scalar 1 0 1 != 1111 01 VLDR (immediate) Half-precision scalar 1 0 1 != 1111 10 VLDR (immediate) Single-precision scalar 1 0 1 != 1111 11 VLDR (immediate) Double-precision scalar 1 0 1 0 10 VSTM, VSTMDB, VSTMIA Decrement Before 1 0 1 0 11 xxxxxxx0 VSTM, VSTMDB, VSTMIA Decrement Before 1 0 1 0 11 xxxxxxx1 FSTMDBX, FSTMIAX Decrement Before 1 0 1 1 10 VLDM, VLDMDB, VLDMIA Decrement Before 1 0 1 1 11 xxxxxxx0 VLDM, VLDMDB, VLDMIA Decrement Before 1 0 1 1 11 xxxxxxx1 FLDM*X (FLDMDBX, FLDMIAX) Decrement Before 1 1 1 1x UNALLOCATED 1 1 1 0 1 1 0 1 1 1 Decode fields Instruction page Encoding P:U:W D L Rn CRd cp15 0x1 0 0 0101 0 STC Post-indexed 0x1 0 1 != 1111 0101 0 LDC (immediate) Post-indexed 010 0 0 0101 0 STC Unindexed 010 0 1 != 1111 0101 0 LDC (immediate) Unindexed 1x0 0 0 0101 0 STC Offset 1x0 0 1 != 1111 0101 0 LDC (immediate) Offset 1x1 0 0 0101 0 STC Pre-indexed 1x1 0 1 != 1111 0101 0 LDC (immediate) Pre-indexed != 000 0 0101 1 UNALLOCATED != 000 0 != 0101 UNALLOCATED != 000 0 1 1111 0101 0 LDC (literal) T1 != 000 1 UNALLOCATED 1 1 1 0 1 1 1 0 0 0 0 1 0 0 1 (0) (0) 1 (0) (0) (0) (0) Decode fields Instruction page Encoding op 0 VMOV (between general-purpose register and half-precision) From general-purpose register 1 VMOV (between general-purpose register and half-precision) To general-purpose register 1 1 1 0 1 1 1 0 0 0 0 1 0 1 0 (0) (0) 1 (0) (0) (0) (0) Decode fields Instruction page Encoding op 0 VMOV (between general-purpose register and single-precision) From general-purpose register 1 VMOV (between general-purpose register and single-precision) To general-purpose register 1 1 1 0 1 1 1 0 1 1 1 1 0 1 0 (0) (0) (0) 1 (0) (0) (0) (0) Decode fields Instruction page Encoding L 0 VMSR T1 1 VMRS T1 1 1 1 0 1 1 1 0 1 0 1 1 1 (0) (0) (0) (0) Decode fields Instruction page Encoding opc1 L opc2 1 VMOV (scalar to general-purpose register) T1 0xx 0 VMOV (general-purpose register to scalar) T1 1xx 0 1x UNALLOCATED 1x0 0 0x VDUP (general-purpose register) 64-bit SIMD vector 1x1 0 0x VDUP (general-purpose register) 128-bit SIMD vector 1 1 1 0 1 1 1 0 1 1 1 1 Decode fields Instruction page Encoding L 0 MCR T1 1 MRC T1 1 1 1 0 1 1 1 0 1 1 1 1 0 1 0 Decode fields Instruction page Encoding o1 opc2 size o3 00 UNALLOCATED 0 000 01 0 UNALLOCATED 0 000 01 1 VABS Half-precision scalar 0 000 10 0 VMOV (register) Single-precision scalar 0 000 10 1 VABS Single-precision scalar 0 000 11 0 VMOV (register) Double-precision scalar 0 000 11 1 VABS Double-precision scalar 0 001 01 0 VNEG Half-precision scalar 0 001 01 1 VSQRT Half-precision scalar 0 001 10 0 VNEG Single-precision scalar 0 001 10 1 VSQRT Single-precision scalar 0 001 11 0 VNEG Double-precision scalar 0 001 11 1 VSQRT Double-precision scalar 0 010 01 UNALLOCATED 0 010 10 0 VCVTB Half-precision to single-precision 0 010 10 1 VCVTT Half-precision to single-precision 0 010 11 0 VCVTB Half-precision to double-precision 0 010 11 1 VCVTT Half-precision to double-precision 0 011 01 0 VCVTB (BFloat16) T1 0 011 01 1 VCVTT (BFloat16) T1 0 011 10 0 VCVTB Single-precision to half-precision 0 011 10 1 VCVTT Single-precision to half-precision 0 011 11 0 VCVTB Double-precision to half-precision 0 011 11 1 VCVTT Double-precision to half-precision 0 100 01 0 VCMP Half-precision scalar 0 100 01 1 VCMPE Half-precision scalar 0 100 10 0 VCMP Single-precision scalar 0 100 10 1 VCMPE Single-precision scalar 0 100 11 0 VCMP Double-precision scalar 0 100 11 1 VCMPE Double-precision scalar 0 101 01 0 VCMP Half-precision scalar 0 101 01 1 VCMPE Half-precision scalar 0 101 10 0 VCMP Single-precision scalar 0 101 10 1 VCMPE Single-precision scalar 0 101 11 0 VCMP Double-precision scalar 0 101 11 1 VCMPE Double-precision scalar 0 110 01 0 VRINTR Half-precision scalar 0 110 01 1 VRINTZ (floating-point) Half-precision scalar 0 110 10 0 VRINTR Single-precision scalar 0 110 10 1 VRINTZ (floating-point) Single-precision scalar 0 110 11 0 VRINTR Double-precision scalar 0 110 11 1 VRINTZ (floating-point) Double-precision scalar 0 111 01 0 VRINTX (floating-point) Half-precision scalar 0 111 01 1 UNALLOCATED 0 111 10 0 VRINTX (floating-point) Single-precision scalar 0 111 10 1 VCVT (between double-precision and single-precision) Single-precision to double-precision 0 111 11 0 VRINTX (floating-point) Double-precision scalar 0 111 11 1 VCVT (between double-precision and single-precision) Double-precision to single-precision 1 000 01 VCVT (integer to floating-point, floating-point) Half-precision scalar 1 000 10 VCVT (integer to floating-point, floating-point) Single-precision scalar 1 000 11 VCVT (integer to floating-point, floating-point) Double-precision scalar 1 001 01 UNALLOCATED 1 001 10 UNALLOCATED 1 001 11 0 UNALLOCATED 1 001 11 1 VJCVT T1 1 01x 01 VCVT (between floating-point and fixed-point, floating-point) Half-precision scalar 1 01x 10 VCVT (between floating-point and fixed-point, floating-point) Single-precision scalar 1 01x 11 VCVT (between floating-point and fixed-point, floating-point) Double-precision scalar 1 100 01 0 VCVTR Half-precision scalar 1 100 01 1 VCVT (floating-point to integer, floating-point) Half-precision scalar 1 100 10 0 VCVTR Single-precision scalar 1 100 10 1 VCVT (floating-point to integer, floating-point) Single-precision scalar 1 100 11 0 VCVTR Double-precision scalar 1 100 11 1 VCVT (floating-point to integer, floating-point) Double-precision scalar 1 101 01 0 VCVTR Half-precision scalar 1 101 01 1 VCVT (floating-point to integer, floating-point) Half-precision scalar 1 101 10 0 VCVTR Single-precision scalar 1 101 10 1 VCVT (floating-point to integer, floating-point) Single-precision scalar 1 101 11 0 VCVTR Double-precision scalar 1 101 11 1 VCVT (floating-point to integer, floating-point) Double-precision scalar 1 11x 01 VCVT (between floating-point and fixed-point, floating-point) Half-precision scalar 1 11x 10 VCVT (between floating-point and fixed-point, floating-point) Single-precision scalar 1 11x 11 VCVT (between floating-point and fixed-point, floating-point) Double-precision scalar 1 1 1 0 1 1 1 0 1 1 1 1 0 (0) 0 (0) 0 Decode fields Instruction page Encoding size 00 UNALLOCATED 01 VMOV (immediate) Half-precision scalar 10 VMOV (immediate) Single-precision scalar 11 VMOV (immediate) Double-precision scalar 1 1 1 0 1 1 1 0 1 0 0 Decode fields Instruction page Encoding o0 o1 size o2 0 00 UNALLOCATED 0 00 01 0 VMLA (floating-point) Half-precision scalar 0 00 01 1 VMLS (floating-point) Half-precision scalar 0 00 10 0 VMLA (floating-point) Single-precision scalar 0 00 10 1 VMLS (floating-point) Single-precision scalar 0 00 11 0 VMLA (floating-point) Double-precision scalar 0 00 11 1 VMLS (floating-point) Double-precision scalar 0 01 01 0 VNMLS Half-precision scalar 0 01 01 1 VNMLA Half-precision scalar 0 01 10 0 VNMLS Single-precision scalar 0 01 10 1 VNMLA Single-precision scalar 0 01 11 0 VNMLS Double-precision scalar 0 01 11 1 VNMLA Double-precision scalar 0 10 01 0 VMUL (floating-point) Half-precision scalar 0 10 01 1 VNMUL Half-precision scalar 0 10 10 0 VMUL (floating-point) Single-precision scalar 0 10 10 1 VNMUL Single-precision scalar 0 10 11 0 VMUL (floating-point) Double-precision scalar 0 10 11 1 VNMUL Double-precision scalar 0 11 01 0 VADD (floating-point) Half-precision scalar 0 11 01 1 VSUB (floating-point) Half-precision scalar 0 11 10 0 VADD (floating-point) Single-precision scalar 0 11 10 1 VSUB (floating-point) Single-precision scalar 0 11 11 0 VADD (floating-point) Double-precision scalar 0 11 11 1 VSUB (floating-point) Double-precision scalar 1 00 01 0 VDIV Half-precision scalar 1 00 10 0 VDIV Single-precision scalar 1 00 11 0 VDIV Double-precision scalar 1 00 != 00 1 UNALLOCATED 1 01 01 0 VFNMS Half-precision scalar 1 01 01 1 VFNMA Half-precision scalar 1 01 10 0 VFNMS Single-precision scalar 1 01 10 1 VFNMA Single-precision scalar 1 01 11 0 VFNMS Double-precision scalar 1 01 11 1 VFNMA Double-precision scalar 1 10 01 0 VFMA Half-precision scalar 1 10 01 1 VFMS Half-precision scalar 1 10 10 0 VFMA Single-precision scalar 1 10 10 1 VFMS Single-precision scalar 1 10 11 0 VFMA Double-precision scalar 1 10 11 1 VFMS Double-precision scalar 1 != 11 00 UNALLOCATED 1 1 1 1 1 1 0 1 0 Decode fields Instruction page Encoding op1 op2 op3 op4 Q U 0 1 0 UNALLOCATED 1x 0 0 0 0 VCMLA 64-bit SIMD vector 1x 0 0 1 0 VCMLA 128-bit SIMD vector x0 0x 0 0 0 UNALLOCATED x1 0x 0 0 0 0 VCADD 64-bit SIMD vector x1 0x 0 0 1 0 VCADD 128-bit SIMD vector 0x x1 1 0 UNALLOCATED 0x 0x 1 UNALLOCATED 0x 1x 0 1 1 UNALLOCATED 0x 10 1 0 0 0 UNALLOCATED 0x 11 1 1 UNALLOCATED 00 00 1 0 0 0 UNALLOCATED 00 00 1 0 1 0 VMMLA T1 00 00 1 1 0 0 VDOT (vector) 64-bit SIMD vector 00 00 1 1 1 0 VDOT (vector) 128-bit SIMD vector 00 10 0 0 0 1 VFMAL (vector) 64-bit SIMD vector 00 10 0 0 1 1 VFMAL (vector) 128-bit SIMD vector 00 10 1 0 0 1 UNALLOCATED 00 10 1 0 1 0 VSMMLA T1 00 10 1 0 1 1 VUMMLA T1 00 10 1 1 0 0 VSDOT (vector) 64-bit SIMD vector 00 10 1 1 0 1 VUDOT (vector) 64-bit SIMD vector 00 10 1 1 1 0 VSDOT (vector) 128-bit SIMD vector 00 10 1 1 1 1 VUDOT (vector) 128-bit SIMD vector 00 11 0 0 1 VFMAB, VFMAT (BFloat16, vector) T1 01 00 1 0 UNALLOCATED 01 10 0 0 0 1 VFMSL (vector) 64-bit SIMD vector 01 10 0 0 1 1 VFMSL (vector) 128-bit SIMD vector 01 10 1 1 UNALLOCATED 01 10 1 0 1 0 VUSMMLA T1 01 10 1 1 0 0 VUSDOT (vector) 64-bit SIMD vector 01 10 1 1 1 0 VUSDOT (vector) 128-bit SIMD vector 01 11 0 0 1 UNALLOCATED 1x 0 1 UNALLOCATED 1x 1 UNALLOCATED 1 1 1 1 1 1 1 0 0 1 0 != 00 0 0 Decode fields Instruction page Encoding cc size 00 01 VSELEQ, VSELGE, VSELGT, VSELVS Equal, half-precision scalar 00 10 VSELEQ, VSELGE, VSELGT, VSELVS Equal, single-precision scalar 00 11 VSELEQ, VSELGE, VSELGT, VSELVS Equal, double-precision scalar 01 01 VSELEQ, VSELGE, VSELGT, VSELVS Unordered, half-precision scalar 01 10 VSELEQ, VSELGE, VSELGT, VSELVS Unordered, single-precision scalar 01 11 VSELEQ, VSELGE, VSELGT, VSELVS Unordered, double-precision scalar 10 01 VSELEQ, VSELGE, VSELGT, VSELVS Greater than or Equal, half-precision scalar 10 10 VSELEQ, VSELGE, VSELGT, VSELVS Greater than or Equal, single-precision scalar 10 11 VSELEQ, VSELGE, VSELGT, VSELVS Greater than or Equal, double-precision scalar 11 01 VSELEQ, VSELGE, VSELGT, VSELVS Greater than, half-precision scalar 11 10 VSELEQ, VSELGE, VSELGT, VSELVS Greater than, single-precision scalar 11 11 VSELEQ, VSELGE, VSELGT, VSELVS Greater than, double-precision scalar 1 1 1 1 1 1 1 0 1 0 0 1 0 != 00 0 Decode fields Instruction page Encoding size op 01 0 VMAXNM Half-precision scalar 01 1 VMINNM Half-precision scalar 10 0 VMAXNM Single-precision scalar 10 1 VMINNM Single-precision scalar 11 0 VMAXNM Double-precision scalar 11 1 VMINNM Double-precision scalar 1 1 1 1 1 1 1 0 1 1 1 0 0 0 0 1 0 != 00 1 0 Decode fields Instruction page Encoding size op x1 UNALLOCATED 10 0 VMOVX T1 10 1 VINS T1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 != 00 1 0 Decode fields Instruction page Encoding op1 RM size op 0 != 00 1 UNALLOCATED 0 00 01 0 VRINTA (floating-point) Half-precision scalar 0 00 10 0 VRINTA (floating-point) Single-precision scalar 0 00 11 0 VRINTA (floating-point) Double-precision scalar 0 01 01 0 VRINTN (floating-point) Half-precision scalar 0 01 10 0 VRINTN (floating-point) Single-precision scalar 0 01 11 0 VRINTN (floating-point) Double-precision scalar 0 10 01 0 VRINTP (floating-point) Half-precision scalar 0 10 10 0 VRINTP (floating-point) Single-precision scalar 0 10 11 0 VRINTP (floating-point) Double-precision scalar 0 11 01 0 VRINTM (floating-point) Half-precision scalar 0 11 10 0 VRINTM (floating-point) Single-precision scalar 0 11 11 0 VRINTM (floating-point) Double-precision scalar 1 00 01 VCVTA (floating-point) Half-precision scalar 1 00 10 VCVTA (floating-point) Single-precision scalar 1 00 11 VCVTA (floating-point) Double-precision scalar 1 01 01 VCVTN (floating-point) Half-precision scalar 1 01 10 VCVTN (floating-point) Single-precision scalar 1 01 11 VCVTN (floating-point) Double-precision scalar 1 10 01 VCVTP (floating-point) Half-precision scalar 1 10 10 VCVTP (floating-point) Single-precision scalar 1 10 11 VCVTP (floating-point) Double-precision scalar 1 11 01 VCVTM (floating-point) Half-precision scalar 1 11 10 VCVTM (floating-point) Single-precision scalar 1 11 11 VCVTM (floating-point) Double-precision scalar 1 1 1 1 1 1 1 0 1 0 0 0 Decode fields Instruction page Encoding op1 op2 Q U 0 0 0 VCMLA (by element) 64-bit SIMD vector of half-precision floating-point 0 1 0 VCMLA (by element) 128-bit SIMD vector of half-precision floating-point 0 00 0 1 VFMAL (by scalar) 64-bit SIMD vector 0 00 1 1 VFMAL (by scalar) 128-bit SIMD vector 0 01 0 1 VFMSL (by scalar) 64-bit SIMD vector 0 01 1 1 VFMSL (by scalar) 128-bit SIMD vector 0 10 1 UNALLOCATED 0 11 1 VFMAB, VFMAT (BFloat16, by scalar) T1 1 1 UNALLOCATED 1 0 0 VCMLA (by element) 64-bit SIMD vector of single-precision floating-point 1 1 0 VCMLA (by element) 128-bit SIMD vector of single-precision floating-point 1 1 1 1 1 1 1 0 1 1 0 Decode fields Instruction page Encoding op1 op2 op4 Q U x0 0 UNALLOCATED x1 UNALLOCATED 0 00 1 1 UNALLOCATED 0 00 1 0 0 VDOT (by element) 64-bit SIMD vector 0 00 1 1 0 VDOT (by element) 128-bit SIMD vector 0 10 1 0 0 VSDOT (by element) 64-bit SIMD vector 0 10 1 0 1 VUDOT (by element) 64-bit SIMD vector 0 10 1 1 0 VSDOT (by element) 128-bit SIMD vector 0 10 1 1 1 VUDOT (by element) 128-bit SIMD vector 1 00 1 0 0 VUSDOT (by element) 64-bit SIMD vector 1 00 1 0 1 VSUDOT (by element) 64-bit SIMD vector 1 00 1 1 0 VUSDOT (by element) 128-bit SIMD vector 1 00 1 1 1 VSUDOT (by element) 128-bit SIMD vector 1 10 1 UNALLOCATED