VACLT
Vector Absolute Compare Less Than
Vector Absolute Compare Less Than takes the absolute value of each element in a vector, and compares it with the absolute value of the corresponding element of a second vector. If the first is less than the second, the corresponding element in the destination vector is set to all ones. Otherwise, it is set to all zeros.
VACGT
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
0
VACLT{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>
VACGT{<c>}{<q>}.<dt> <Dd>, <Dm>, <Dn>
Never
1
VACLT{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>
VACGT{<c>}{<q>}.<dt> <Qd>, <Qm>, <Qn>
Never
1
1
1
1
1
1
1
1
0
1
1
1
1
0
1
0
VACLT{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>
VACGT{<c>}{<q>}.<dt> <Dd>, <Dm>, <Dn>
Never
1
VACLT{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>
VACGT{<c>}{<q>}.<dt> <Qd>, <Qm>, <Qn>
Never
<c>
For the "A1 128-bit SIMD vector" and "A1 64-bit SIMD vector" variants: see Standard assembler syntax fields. This encoding must be unconditional.
<c>
For the "T1 128-bit SIMD vector" and "T1 64-bit SIMD vector" variants: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<dt>
Is the data type for the elements of the vectors,
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
<Dn>
Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.
<Dm>
Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.
<Qd>
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.
<Qn>
Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.
<Qm>
Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.
2026-03-26 20:27:25
2026-03_rel