VBIC (immediate)
Vector Bitwise Bit Clear (immediate)
Vector Bitwise Bit Clear (immediate) performs a bitwise AND between
a register value and the complement of an immediate value, and
returns the result into the destination vector.
Depending on settings in the CPACR,
NSACR, and
HCPTR registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information see Enabling Advanced
SIMD and floating-point support.
Related encodings: See Advanced SIMD one register and modified immediate for the T32 instruction set, or Advanced SIMD one register and modified immediate for the A32 instruction set.
The I8, I64, and F32 data types are permitted as pseudo-instructions, if the immediate can be represented by this instruction, and are encoded using a permitted encoding of the I16 or I32 data type.
This instruction is a data-independent-time instruction as described in About the DIT bit.
This instruction is used by the alias
VAND (immediate)
Never
See
below for details of when the alias is preferred.
It has encodings from the following instruction sets:
A32 (
A1
and
A2
)
and
T32 (
T1
and
T2
)
.
1
1
1
1
0
0
1
1
0
0
0
0
x
x
1
0
1
1
0
VBIC{<c>}{<q>}.I32 {<Dd>, }<Dd>, #<imm>
1
VBIC{<c>}{<q>}.I32 {<Qd>, }<Qd>, #<imm>
if cmode[0] == '0' || cmode[3:2] == '11' then See("Related encodings"); end;
if Q == '1' && Vd[0] == '1' then Undefined(); end;
let imm64 : bits(64) = AdvSIMDExpandImm('1', cmode, i::imm3::imm4);
let d : integer = UInt(D::Vd);
let regs : integer = if Q == '0' then 1 else 2;
1
1
1
1
0
0
1
1
0
0
0
1
0
x
1
0
1
1
0
VBIC{<c>}{<q>}.I16 {<Dd>, }<Dd>, #<imm>
1
VBIC{<c>}{<q>}.I16 {<Qd>, }<Qd>, #<imm>
if cmode[0] == '0' || cmode[3:2] == '11' then See("Related encodings"); end;
if Q == '1' && Vd[0] == '1' then Undefined(); end;
let imm64 : bits(64) = AdvSIMDExpandImm('1', cmode, i::imm3::imm4);
let d : integer = UInt(D::Vd);
let regs : integer = if Q == '0' then 1 else 2;
1
1
1
1
1
1
1
1
0
0
0
0
x
x
1
0
1
1
0
VBIC{<c>}{<q>}.I32 {<Dd>, }<Dd>, #<imm>
1
VBIC{<c>}{<q>}.I32 {<Qd>, }<Qd>, #<imm>
if cmode[0] == '0' || cmode[3:2] == '11' then See("Related encodings"); end;
if Q == '1' && Vd[0] == '1' then Undefined(); end;
let imm64 : bits(64) = AdvSIMDExpandImm('1', cmode, i::imm3::imm4);
let d : integer = UInt(D::Vd);
let regs : integer = if Q == '0' then 1 else 2;
1
1
1
1
1
1
1
1
0
0
0
1
0
x
1
0
1
1
0
VBIC{<c>}{<q>}.I16 {<Dd>, }<Dd>, #<imm>
1
VBIC{<c>}{<q>}.I16 {<Qd>, }<Qd>, #<imm>
if cmode[0] == '0' || cmode[3:2] == '11' then See("Related encodings"); end;
if Q == '1' && Vd[0] == '1' then Undefined(); end;
let imm64 : bits(64) = AdvSIMDExpandImm('1', cmode, i::imm3::imm4);
let d : integer = UInt(D::Vd);
let regs : integer = if Q == '0' then 1 else 2;
<c>
For the "A1 128-bit SIMD vector", "A1 64-bit SIMD vector", "A2 128-bit SIMD vector", and "A2 64-bit SIMD vector" variants: see Standard assembler syntax fields. This encoding must be unconditional.
<c>
For the "T1 128-bit SIMD vector", "T1 64-bit SIMD vector", "T2 128-bit SIMD vector", and "T2 64-bit SIMD vector" variants: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
<imm>
Is a constant of the specified type that is replicated to fill the destination register. For details of the range of constants available and the encoding of <imm>, see Modified immediate constants in T32 and A32 Advanced SIMD instructions.
<Qd>
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.
Alias Conditions
if ConditionPassed() then
EncodingSpecificOperations();
CheckAdvSIMDEnabled();
for r = 0 to regs-1 do
D(d+r) = D(d+r) AND NOT(imm64);
end;
end;
2026-03-26 20:27:25
2026-03_rel