VCADD
Vector Complex Add
Vector Complex Add.
This instruction operates on complex numbers that are represented in SIMD&FP registers as pairs of
elements, with the more significant element holding the imaginary part of the number and the less
significant element holding the real part of the number. Each element holds a floating-point
value. It performs the following calculation on the corresponding complex number element pairs
from the two source registers:
Considering the complex number from the second source register on an Argand diagram, the number is rotated counterclockwise by 90 or 270 degrees.
The rotated complex number is added to the complex number from the first source register.
Depending on settings in the CPACR,
NSACR, and
HCPTR registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information see Enabling Advanced
SIMD and floating-point support.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
1
1
1
1
1
1
0
1
0
1
0
0
0
0
0
VCADD{<q>}.<dt> <Dd>, <Dn>, <Dm>, #<rotate>
1
VCADD{<q>}.<dt> <Qd>, <Qn>, <Qm>, #<rotate>
if !IsFeatureImplemented(FEAT_FCMA) then Undefined(); end;
if Q == '1' && (Vd[0] == '1' || Vn[0] == '1' || Vm[0] == '1') then Undefined(); end;
if S == '0' && !IsFeatureImplemented(FEAT_FP16) then Undefined(); end;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
let esize : integer{} = 16 << UInt(S);
let elements : integer = 64 DIV esize;
let regs : integer = if Q == '0' then 1 else 2;
1
1
1
1
1
1
0
1
0
1
0
0
0
0
0
VCADD{<q>}.<dt> <Dd>, <Dn>, <Dm>, #<rotate>
1
VCADD{<q>}.<dt> <Qd>, <Qn>, <Qm>, #<rotate>
if InITBlock() then UnpredictableProcedure(); end;
if !IsFeatureImplemented(FEAT_FCMA) then Undefined(); end;
if Q == '1' && (Vd[0] == '1' || Vn[0] == '1' || Vm[0] == '1') then Undefined(); end;
if S == '0' && !IsFeatureImplemented(FEAT_FP16) then Undefined(); end;
let esize : integer{} = 16 << UInt(S);
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
let elements : integer = 64 DIV esize;
let regs : integer = if Q == '0' then 1 else 2;
<q>
See Standard assembler syntax fields.
<dt>
Is the data type for the elements of the vectors,
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
<Dn>
Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.
<Dm>
Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.
<rotate>
Is the rotation to be applied to elements in the second SIMD&FP source register,
<Qd>
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.
<Qn>
Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.
<Qm>
Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.
EncodingSpecificOperations();
CheckAdvSIMDEnabled();
for r = 0 to regs-1 do
let operand1 : bits(64) = D(n+r);
let operand2 : bits(64) = D(m+r);
let fpcr : FPCR_Type = StandardFPCR();
for e = 0 to (elements DIV 2)-1 do
var element1 : bits(esize);
var element3 : bits(esize);
case rot of
when '0' =>
element1 = FPNeg{esize}(operand2[(e*2+1)*:esize], fpcr);
element3 = operand2[(e*2)*:esize];
when '1' =>
element1 = operand2[(e*2+1)*:esize];
element3 = FPNeg{esize}(operand2[(e*2)*:esize], fpcr);
end;
let result1 : bits(esize) = FPAdd{}(operand1[(e*2)*:esize],element1,fpcr);
let result2 : bits(esize) = FPAdd{}(operand1[(e*2+1)*:esize],element3,fpcr);
D(d+r)[(e*2)*:esize] = result1;
D(d+r)[(e*2+1)*:esize] = result2;
end;
end;
2026-03-26 20:27:25
2026-03_rel