VCLS
Vector Count Leading Sign Bits
Vector Count Leading Sign Bits determines the number of consecutive
bits following the topmost bit, that are the same as the topmost
bit, in each element in a vector, and places the results in a second
vector. The result does not include the topmost bit itself.
The operand vector elements can be any one of 8-bit, 16-bit,
or 32-bit signed integers.
The result vector elements are the same data type as the operand
vector elements.
Depending on settings in the CPACR,
NSACR, and
HCPTR registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information see Enabling Advanced
SIMD and floating-point support.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
1
1
1
1
0
0
1
1
1
1
1
0
0
0
1
0
0
0
0
0
VCLS{<c>}{<q>}.<dt> <Dd>, <Dm>
1
VCLS{<c>}{<q>}.<dt> <Qd>, <Qm>
if size == '11' then Undefined(); end;
if Q == '1' && (Vd[0] == '1' || Vm[0] == '1') then Undefined(); end;
let esize : integer{} = 8 << UInt(size);
let elements : integer = 64 DIV esize;
let d : integer = UInt(D::Vd);
let m : integer = UInt(M::Vm);
let regs : integer = if Q == '0' then 1 else 2;
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
0
0
VCLS{<c>}{<q>}.<dt> <Dd>, <Dm>
1
VCLS{<c>}{<q>}.<dt> <Qd>, <Qm>
if size == '11' then Undefined(); end;
if Q == '1' && (Vd[0] == '1' || Vm[0] == '1') then Undefined(); end;
let esize : integer{} = 8 << UInt(size);
let elements : integer = 64 DIV esize;
let d : integer = UInt(D::Vd);
let m : integer = UInt(M::Vm);
let regs : integer = if Q == '0' then 1 else 2;
<c>
For the "A1 128-bit SIMD vector" and "A1 64-bit SIMD vector" variants: see Standard assembler syntax fields. This encoding must be unconditional.
<c>
For the "T1 128-bit SIMD vector" and "T1 64-bit SIMD vector" variants: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<dt>
Is the data type for the elements of the operands,
size
<dt>
00
S8
01
S16
10
S32
11
RESERVED
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
<Dm>
Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.
<Qd>
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.
<Qm>
Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.
if ConditionPassed() then
EncodingSpecificOperations();
CheckAdvSIMDEnabled();
for r = 0 to regs-1 do
for e = 0 to elements-1 do
D(d+r)[e*:esize] = CountLeadingSignBits(D(m+r)[e*:esize])[esize-1:0];
end;
end;
end;
2026-03-26 20:27:25
2026-03_rel