VCVT (from single-precision to BFloat16, Advanced SIMD)
Vector Convert from single-precision to BFloat16
Vector Convert from single-precision to BFloat16
converts each 32-bit element in a vector from single-precision
floating-point to BFloat16 format, and writes the result into a
second vector. The result vector elements are half the width of the
source vector elements.
Unlike the BFloat16 multiplication instructions, this instruction
uses the Round to Nearest rounding mode, and can generate a
floating-point exception that causes cumulative exception bits in the
FPSCR to be set.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
1
1
1
1
0
0
1
1
1
1
1
0
1
1
0
0
1
1
0
0
1
0
VCVT{<c>}{<q>}.BF16.F32 <Dd>, <Qm>
if !IsFeatureImplemented(FEAT_AA32BF16) then Undefined(); end;
if Vm[0] == '1' then Undefined(); end;
let d : integer = UInt(D::Vd);
let m : integer = UInt(M::Vm);
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
1
1
0
0
1
0
VCVT{<c>}{<q>}.BF16.F32 <Dd>, <Qm>
if !IsFeatureImplemented(FEAT_AA32BF16) then Undefined(); end;
if Vm[0] == '1' then Undefined(); end;
let d : integer = UInt(D::Vd);
let m : integer = UInt(M::Vm);
<c>
For the "A1" variant: see Standard assembler syntax fields. This encoding must be unconditional.
<c>
For the "T1" variant: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
<Qm>
Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.
var operand : bits(128);
var result : bits(64);
if ConditionPassed() then
EncodingSpecificOperations();
CheckAdvSIMDEnabled();
let fpcr : FPCR_Type = StandardFPCR();
operand = Q(m>>1);
for e = 0 to 3 do
let op : bits(32) = operand[e*:32];
result[e*:16] = FPConvertBF(op, fpcr);
end;
D(d) = result;
end;
2026-03-26 20:27:25
2026-03_rel