VCVT (between half-precision and single-precision, Advanced SIMD)
Vector Convert between half-precision and single-precision
Vector Convert between half-precision and single-precision converts
each element in a vector from single-precision to half-precision
floating-point, or from half-precision to single-precision, and
places the results in a second vector.
Depending on settings in the CPACR,
NSACR, and
HCPTR registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information see Enabling Advanced
SIMD and floating-point support.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
1
1
1
1
0
0
1
1
1
1
1
1
0
0
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1
0
0
0
1
VCVT{<c>}{<q>}.F32.F16 <Qd>, <Dm>
0
VCVT{<c>}{<q>}.F16.F32 <Dd>, <Qm>
if size != '01' then Undefined(); end;
if op == '1' && Vd[0] == '1' then Undefined(); end;
if op == '0' && Vm[0] == '1' then Undefined(); end;
let half_to_single : boolean = (op == '1');
let esize : integer{} = 16;
let elements : integer = 4;
let m : integer = UInt(M::Vm);
let d : integer = UInt(D::Vd);
1
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0
0
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0
0
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1
VCVT{<c>}{<q>}.F32.F16 <Qd>, <Dm>
0
VCVT{<c>}{<q>}.F16.F32 <Dd>, <Qm>
if size != '01' then Undefined(); end;
if op == '1' && Vd[0] == '1' then Undefined(); end;
if op == '0' && Vm[0] == '1' then Undefined(); end;
let half_to_single : boolean = (op == '1');
let esize : integer{} = 16;
let elements : integer = 4;
let m : integer = UInt(M::Vm);
let d : integer = UInt(D::Vd);
<c>
For the "A1 Half-precision to single-precision" and "A1 Single-precision to half-precision" variants: see Standard assembler syntax fields. This encoding must be unconditional.
<c>
For the "T1 Half-precision to single-precision" and "T1 Single-precision to half-precision" variants: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Qd>
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.
<Dm>
Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
<Qm>
Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.
if ConditionPassed() then
EncodingSpecificOperations();
CheckAdvSIMDEnabled();
let fpcr : FPCR_Type = StandardFPCR();
for e = 0 to elements-1 do
if half_to_single then
Q(d>>1)[e*:32] = FPConvert{32, 16}(Din(m)[e*:16], fpcr);
else
D(d)[e*:16] = FPConvert{16, 32}(Qin(m>>1)[e*:32], fpcr);
end;
end;
end;
2026-03-26 20:27:25
2026-03_rel