VCVT (between floating-point and integer, Advanced SIMD)
Vector Convert between floating-point and integer
Vector Convert between floating-point and integer converts each
element in a vector from floating-point to integer, or from integer
to floating-point, and places the results in a second vector.
The vector elements are the same type, and are floating-point numbers or integers.
Signed and unsigned integers are distinct.
The floating-point to integer operation uses the Round towards Zero
rounding mode. The integer to floating-point operation uses the
Round to Nearest rounding mode.
Depending on settings in the CPACR,
NSACR, and
HCPTR registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information see Enabling Advanced
SIMD and floating-point support.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
1
1
1
1
0
0
1
1
1
1
1
1
1
0
1
1
0
0
VCVT{<c>}{<q>}.<dt1>.<dt2> <Dd>, <Dm>
1
VCVT{<c>}{<q>}.<dt1>.<dt2> <Qd>, <Qm>
if Q == '1' && (Vd[0] == '1' || Vm[0] == '1') then Undefined(); end;
if size IN {'00', '11'} then Undefined(); end;
if size == '01' && !IsFeatureImplemented(FEAT_FP16) then Undefined(); end;
let to_integer : boolean = (op[1] == '1');
let unsigned : boolean = (op[0] == '1');
let esize : integer{} = 8 << UInt(size);
let elements : integer = 64 DIV esize;
let d : integer = UInt(D::Vd);
let m : integer = UInt(M::Vm);
let regs : integer = if Q == '0' then 1 else 2;
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
VCVT{<c>}{<q>}.<dt1>.<dt2> <Dd>, <Dm>
1
VCVT{<c>}{<q>}.<dt1>.<dt2> <Qd>, <Qm>
if Q == '1' && (Vd[0] == '1' || Vm[0] == '1') then Undefined(); end;
if size IN {'00', '11'} then Undefined(); end;
if size == '01' && !IsFeatureImplemented(FEAT_FP16) then Undefined(); end;
if size == '01' && InITBlock() then UnpredictableProcedure(); end;
let to_integer : boolean = (op[1] == '1');
let unsigned : boolean = (op[0] == '1');
let esize : integer{} = 8 << UInt(size);
let elements : integer = 64 DIV esize;
let d : integer = UInt(D::Vd);
let m : integer = UInt(M::Vm);
let regs : integer = if Q == '0' then 1 else 2;
size == '01' && InITBlock()
The instruction executes as if it passes the Condition code check.
The instruction executes as NOP. This means it behaves as if it fails the Condition code check.
<c>
For the "A1 128-bit SIMD vector" and "A1 64-bit SIMD vector" variants: see Standard assembler syntax fields. This encoding must be unconditional.
<c>
For the "T1 128-bit SIMD vector" and "T1 64-bit SIMD vector" variants: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<dt1>
Is the data type for the elements of the destination vector,
size
op
<dt1>
01
0x
F16
01
10
S16
01
11
U16
10
0x
F32
10
10
S32
10
11
U32
<dt2>
Is the data type for the elements of the source vector,
size
op
<dt2>
01
00
S16
01
01
U16
01
1x
F16
10
00
S32
10
01
U32
10
1x
F32
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
<Dm>
Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.
<Qd>
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.
<Qm>
Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.
if ConditionPassed() then
EncodingSpecificOperations();
CheckAdvSIMDEnabled();
let fpcr : FPCR_Type = StandardFPCR();
var result : bits(esize);
for r = 0 to regs-1 do
for e = 0 to elements-1 do
let operand1 : bits(esize) = D(m+r)[e*:esize];
if to_integer then
result = FPToFixed{esize, esize}(operand1, 0, unsigned, fpcr, FPRounding_ZERO);
else
result = FixedToFP{esize, esize}(operand1, 0, unsigned, fpcr, FPRounding_TIEEVEN);
end;
D(d+r)[e*:esize] = result;
end;
end;
end;
2026-03-26 20:27:25
2026-03_rel