VCVT (between floating-point and fixed-point, Advanced SIMD)
Vector Convert between floating-point and fixed-point
Vector Convert between floating-point and fixed-point converts each
element in a vector from floating-point to fixed-point, or from
fixed-point to floating-point, and places the results in a second
vector.
The vector elements are the same type, and are floating-point numbers or integers.
Signed and unsigned integers are distinct.
The floating-point to fixed-point operation uses the Round towards
Zero rounding mode. The fixed-point to floating-point operation uses
the Round to Nearest rounding mode.
Depending on settings in the CPACR,
NSACR, and
HCPTR registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information see Enabling Advanced
SIMD and floating-point support.
Related encodings: See Advanced SIMD one register and modified immediate for the T32 instruction set, or Advanced SIMD one register and modified immediate for the A32 instruction set.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
1
1
1
1
0
0
1
1
!= 000xxx
1
1
0
1
0
VCVT{<c>}{<q>}.<dt1>.<dt2> <Dd>, <Dm>, #<fbits>
1
VCVT{<c>}{<q>}.<dt1>.<dt2> <Qd>, <Qm>, #<fbits>
if imm6 == '000xxx' then See("Related encodings"); end;
if op[1] == '0' && !IsFeatureImplemented(FEAT_FP16) then Undefined(); end;
if op[1] == '0' && imm6 == '10xxxx' then Undefined(); end;
if imm6 == '0xxxxx' then Undefined(); end;
if Q == '1' && (Vd[0] == '1' || Vm[0] == '1') then Undefined(); end;
let to_fixed : boolean = (op[0] == '1');
let frac_bits : integer = 64 - UInt(imm6);
let unsigned : boolean = (U == '1');
let esize : integer{} = 16 << UInt(op[1]);
let elements : integer = 64 DIV esize;
let d : integer = UInt(D::Vd);
let m : integer = UInt(M::Vm);
let regs : integer = if Q == '0' then 1 else 2;
1
1
1
1
1
1
1
1
!= 000xxx
1
1
0
1
0
VCVT{<c>}{<q>}.<dt1>.<dt2> <Dd>, <Dm>, #<fbits>
1
VCVT{<c>}{<q>}.<dt1>.<dt2> <Qd>, <Qm>, #<fbits>
if imm6 == '000xxx' then See("Related encodings"); end;
if op[1] == '0' && !IsFeatureImplemented(FEAT_FP16) then Undefined(); end;
if op[1] == '0' && imm6 == '10xxxx' then Undefined(); end;
if imm6 == '0xxxxx' then Undefined(); end;
if Q == '1' && (Vd[0] == '1' || Vm[0] == '1') then Undefined(); end;
let to_fixed : boolean = (op[0] == '1');
let frac_bits : integer = 64 - UInt(imm6);
let unsigned : boolean = (U == '1');
let esize : integer{} = 16 << UInt(op[1]);
let elements : integer = 64 DIV esize;
let d : integer = UInt(D::Vd);
let m : integer = UInt(M::Vm);
let regs : integer = if Q == '0' then 1 else 2;
<c>
For the "A1 128-bit SIMD vector" and "A1 64-bit SIMD vector" variants: see Standard assembler syntax fields. This encoding must be unconditional.
<c>
For the "T1 128-bit SIMD vector" and "T1 64-bit SIMD vector" variants: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<dt1>
Is the data type for the elements of the destination vector,
op
U
<dt1>
00
x
F16
01
0
S16
01
1
U16
10
x
F32
11
0
S32
11
1
U32
<dt2>
Is the data type for the elements of the source vector,
op
U
<dt2>
00
0
S16
00
1
U16
01
x
F16
10
0
S32
10
1
U32
11
x
F32
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
<Dm>
Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.
<fbits>
The number of fraction bits in the fixed point number, in the range 1 to 32 for 32-bit elements, or in the range 1 to 16 for 16-bit elements:
(64 - <fbits>) is encoded in imm6.
An assembler can permit an <fbits> value of 0. This is encoded as floating-point to integer or integer to floating-point instruction, see VCVT (between floating-point and integer, Advanced SIMD).
<Qd>
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.
<Qm>
Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.
if ConditionPassed() then
EncodingSpecificOperations();
CheckAdvSIMDEnabled();
var result : bits(esize);
let fpcr : FPCR_Type = StandardFPCR();
for r = 0 to regs-1 do
for e = 0 to elements-1 do
let operand1 : bits(esize) = D(m+r)[e*:esize];
if to_fixed then
result = FPToFixed{esize, esize}(operand1, frac_bits, unsigned, fpcr,
FPRounding_ZERO);
else
result = FixedToFP{esize, esize}(operand1, frac_bits, unsigned, fpcr,
FPRounding_TIEEVEN);
end;
D(d+r)[e*:esize] = result;
end;
end;
end;
2026-03-26 20:27:25
2026-03_rel