VCVT (between floating-point and fixed-point, floating-point)
Convert between floating-point and fixed-point
Convert between floating-point and fixed-point converts a value in a
register from floating-point to fixed-point, or from fixed-point to
floating-point. Software can specify the fixed-point value as either
signed or unsigned.
The fixed-point value can be 16-bit or 32-bit. Conversions from
fixed-point values take their operand from the low-order bits of the
source register and ignore any remaining bits. Signed conversions to
fixed-point values sign-extend the result value to the destination
register width. Unsigned conversions to fixed-point values
zero-extend the result value to the destination register width.
The floating-point to fixed-point operation uses the Round towards
Zero rounding mode. The fixed-point to floating-point operation uses
the Round to Nearest rounding mode.
Depending on settings in the CPACR,
NSACR,
HCPTR, and
FPEXC registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information see Enabling Advanced
SIMD and floating-point support.
For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly VCVT (between floating-point and fixed-point).
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
!= 1111
1
1
1
0
1
1
1
1
1
1
0
1
0
0
0
1
VCVT{<c>}{<q>}.F16.<dt> <Sdm>, <Sdm>, #<fbits>
1
0
1
VCVT{<c>}{<q>}.<dt>.F16 <Sdm>, <Sdm>, #<fbits>
0
1
0
VCVT{<c>}{<q>}.F32.<dt> <Sdm>, <Sdm>, #<fbits>
1
1
0
VCVT{<c>}{<q>}.<dt>.F32 <Sdm>, <Sdm>, #<fbits>
0
1
1
VCVT{<c>}{<q>}.F64.<dt> <Ddm>, <Ddm>, #<fbits>
1
1
1
VCVT{<c>}{<q>}.<dt>.F64 <Ddm>, <Ddm>, #<fbits>
if sf == '00' || (sf == '01' && !IsFeatureImplemented(FEAT_FP16)) then Undefined(); end;
if sf == '01' && cond != '1110' then UnpredictableProcedure(); end;
let to_fixed : boolean = (op == '1');
let unsigned : boolean = (U == '1');
let size : integer{} = if sx == '0' then 16 else 32;
let frac_bits : integer = size - UInt(imm4::i);
let fp_size : integer = 8 << UInt(sf);
let d : integer = if sf == '11' then UInt(D::Vd) else UInt(Vd::D);
if frac_bits < 0 then UnpredictableProcedure(); end;
frac_bits < 0
1
1
1
0
1
1
1
0
1
1
1
1
1
1
0
1
0
0
0
1
VCVT{<c>}{<q>}.F16.<dt> <Sdm>, <Sdm>, #<fbits>
1
0
1
VCVT{<c>}{<q>}.<dt>.F16 <Sdm>, <Sdm>, #<fbits>
0
1
0
VCVT{<c>}{<q>}.F32.<dt> <Sdm>, <Sdm>, #<fbits>
1
1
0
VCVT{<c>}{<q>}.<dt>.F32 <Sdm>, <Sdm>, #<fbits>
0
1
1
VCVT{<c>}{<q>}.F64.<dt> <Ddm>, <Ddm>, #<fbits>
1
1
1
VCVT{<c>}{<q>}.<dt>.F64 <Ddm>, <Ddm>, #<fbits>
if sf == '00' || (sf == '01' && !IsFeatureImplemented(FEAT_FP16)) then Undefined(); end;
if sf == '01' && InITBlock() then UnpredictableProcedure(); end;
let to_fixed : boolean = (op == '1');
let unsigned : boolean = (U == '1');
let size : integer{} = if sx == '0' then 16 else 32;
let frac_bits : integer = size - UInt(imm4::i);
let fp_size : integer = 8 << UInt(sf);
let d : integer = if sf == '11' then UInt(D::Vd) else UInt(Vd::D);
if frac_bits < 0 then UnpredictableProcedure(); end;
frac_bits < 0
<c>
See Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<dt>
Is the data type for the fixed-point number,
U
sx
<dt>
0
0
S16
0
1
S32
1
0
U16
1
1
U32
<Sdm>
Is the 32-bit name of the SIMD&FP destination and source register, encoded in the "Vd:D" field.
<fbits>
The number of fraction bits in the fixed-point number:
If <dt> is S16 or U16, <fbits> must be in the range 0-16. (16 - <fbits>) is encoded in [imm4, i]
If <dt> is S32 or U32, <fbits> must be in the range 1-32. (32 - <fbits>) is encoded in [imm4, i].
<Ddm>
Is the 64-bit name of the SIMD&FP destination and source register, encoded in the "D:Vd" field.
if ConditionPassed() then
EncodingSpecificOperations();
CheckVFPEnabled(TRUE);
let fpcr : FPCR_Type = EffectiveFPCR();
if to_fixed then
var result : bits(size);
case fp_size of
when 16 =>
result = FPToFixed{size, 16}(H(d), frac_bits, unsigned, fpcr, FPRounding_ZERO);
S(d) = Extend{32}(result, unsigned);
when 32 =>
result = FPToFixed{size, 32}(S(d), frac_bits, unsigned, fpcr, FPRounding_ZERO);
S(d) = Extend{32}(result, unsigned);
when 64 =>
result = FPToFixed{size, 64}(D(d), frac_bits, unsigned, fpcr, FPRounding_ZERO);
D(d) = Extend{64}(result, unsigned);
end;
else
case fp_size of
when 16 =>
H(d) = FixedToFP{16, size}(S(d)[size-1:0], frac_bits, unsigned, fpcr,
FPRounding_TIEEVEN);
when 32 =>
S(d) = FixedToFP{32, size}(S(d)[size-1:0], frac_bits, unsigned, fpcr,
FPRounding_TIEEVEN);
when 64 =>
D(d) = FixedToFP{64, size}(D(d)[size-1:0], frac_bits, unsigned, fpcr,
FPRounding_TIEEVEN);
end;
end;
end;
2026-03-26 20:27:25
2026-03_rel