VCVTA (Advanced SIMD)
Vector Convert floating-point to integer with Round to Nearest with Ties to Away
Vector Convert floating-point to integer with Round to Nearest with
Ties to Away converts each element in a vector from floating-point
to integer using the Round to Nearest with Ties to Away rounding
mode, and places the results in a second vector.
The operand vector elements are floating-point numbers.
The result vector elements are integers, and the same size as the
operand vector elements.
Signed and unsigned integers are distinct.
Depending on settings in the CPACR,
NSACR,
HCPTR, and
FPEXC registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information see Enabling Advanced
SIMD and floating-point support.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
1
1
1
1
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
VCVTA{<q>}.<dt>.<dt2> <Dd>, <Dm>
1
VCVTA{<q>}.<dt>.<dt2> <Qd>, <Qm>
if Q == '1' && (Vd[0] == '1' || Vm[0] == '1') then Undefined(); end;
if size IN {'00', '11'} then Undefined(); end;
if size == '01' && !IsFeatureImplemented(FEAT_FP16) then Undefined(); end;
let rounding : FPRounding = FPDecodeRM(RM);
let unsigned : boolean = (op == '1');
let esize : integer{} = 8 << UInt(size);
let elements : integer = 64 DIV esize;
let d : integer = UInt(D::Vd);
let m : integer = UInt(M::Vm);
let regs : integer = if Q == '0' then 1 else 2;
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
VCVTA{<q>}.<dt>.<dt2> <Dd>, <Dm>
1
VCVTA{<q>}.<dt>.<dt2> <Qd>, <Qm>
if InITBlock() then UnpredictableProcedure(); end;
if Q == '1' && (Vd[0] == '1' || Vm[0] == '1') then Undefined(); end;
if size IN {'00', '11'} then Undefined(); end;
if size == '01' && !IsFeatureImplemented(FEAT_FP16) then Undefined(); end;
let rounding : FPRounding = FPDecodeRM(RM);
let unsigned : boolean = (op == '1');
let esize : integer{} = 8 << UInt(size);
let elements : integer = 64 DIV esize;
let d : integer = UInt(D::Vd);
let m : integer = UInt(M::Vm);
let regs : integer = if Q == '0' then 1 else 2;
InITBlock()
The instruction executes as if it passes the Condition code check.
The instruction executes as NOP. This means it behaves as if it fails the Condition code check.
<q>
See Standard assembler syntax fields.
<dt>
Is the data type for the elements of the destination,
op
size
<dt>
0
01
S16
0
10
S32
1
01
U16
1
10
U32
<dt2>
Is the data type for the elements of the source vector,
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
<Dm>
Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.
<Qd>
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.
<Qm>
Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.
EncodingSpecificOperations();
CheckAdvSIMDEnabled();
let fpcr : FPCR_Type = StandardFPCR();
for r = 0 to regs-1 do
for e = 0 to elements-1 do
D(d+r)[e*:esize] = FPToFixed{esize, esize}(D(m+r)[e*:esize],
0, unsigned, fpcr, rounding);
end;
end;
2026-03-26 20:27:25
2026-03_rel