VCVTM (floating-point)
Convert floating-point to integer with Round towards -Infinity
Convert floating-point to integer with Round towards -Infinity
converts a value in a register from floating-point to a 32-bit
integer using the Round towards -Infinity rounding mode, and places
the result in a second register.
Depending on settings in the CPACR,
NSACR,
HCPTR, and
FPEXC registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information see Enabling Advanced
SIMD and floating-point support.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
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VCVTM{<q>}.<dt>.F16 <Sd>, <Sm>
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VCVTM{<q>}.<dt>.F32 <Sd>, <Sm>
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VCVTM{<q>}.<dt>.F64 <Sd>, <Dm>
if size == '00' then Undefined(); end;
if size == '01' && !IsFeatureImplemented(FEAT_FP16) then Undefined(); end;
let rounding : FPRounding = FPDecodeRM(RM);
let unsigned : boolean = (op == '0');
let esize : integer{} = 8 << UInt(size);
let d : integer = UInt(Vd::D);
let m : integer = if size == '11' then UInt(M::Vm) else UInt(Vm::M);
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VCVTM{<q>}.<dt>.F16 <Sd>, <Sm>
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VCVTM{<q>}.<dt>.F32 <Sd>, <Sm>
1
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VCVTM{<q>}.<dt>.F64 <Sd>, <Dm>
if InITBlock() then UnpredictableProcedure(); end;
if size == '00' then Undefined(); end;
if size == '01' && !IsFeatureImplemented(FEAT_FP16) then Undefined(); end;
let rounding : FPRounding = FPDecodeRM(RM);
let unsigned : boolean = (op == '0');
let esize : integer{} = 8 << UInt(size);
let d : integer = UInt(Vd::D);
let m : integer = if size == '11' then UInt(M::Vm) else UInt(Vm::M);
InITBlock()
The instruction executes as if it passes the Condition code check.
The instruction executes as NOP. This means it behaves as if it fails the Condition code check.
<q>
See Standard assembler syntax fields.
<dt>
Is the data type for the elements of the destination,
<Sd>
Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.
<Sm>
Is the 32-bit name of the SIMD&FP source register, encoded in the "Vm:M" field.
<Dm>
Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.
EncodingSpecificOperations();
CheckVFPEnabled(TRUE);
let fpcr : FPCR_Type = EffectiveFPCR();
case esize of
when 16 =>
S(d) = FPToFixed{32, 16}(H(m), 0, unsigned, fpcr, rounding);
when 32 =>
S(d) = FPToFixed{32, 32}(S(m), 0, unsigned, fpcr, rounding);
when 64 =>
S(d) = FPToFixed{32, 64}(D(m), 0, unsigned, fpcr, rounding);
end;
2026-03-26 20:27:25
2026-03_rel