VEXT (byte elements) Vector Extract Vector Extract extracts elements from the bottom end of the second operand vector and the top end of the first, concatenates them and places the result in the destination vector. The elements of the vectors are treated as being 8-bit fields. There is no distinction between data types. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support. This instruction is a data-independent-time instruction as described in About the DIT bit. This instruction is used by the alias VEXT (multibyte elements) Never See below for details of when the alias is preferred. It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) . 1 1 1 1 0 0 1 0 1 1 1 0 0 VEXT{<c>}{<q>}.8 {<Dd>, }<Dn>, <Dm>, #<imm> 1 VEXT{<c>}{<q>}.8 {<Qd>, }<Qn>, <Qm>, #<imm> if Q == '1' && (Vd[0] == '1' || Vn[0] == '1' || Vm[0] == '1') then Undefined(); end; if Q == '0' && imm4[3] == '1' then Undefined(); end; let quadword_operation : boolean = (Q == '1'); let position : integer{} = 8 * UInt(imm4); let d : integer = UInt(D::Vd); let n : integer = UInt(N::Vn); let m : integer = UInt(M::Vm); 1 1 1 0 1 1 1 1 1 1 1 0 0 VEXT{<c>}{<q>}.8 {<Dd>, }<Dn>, <Dm>, #<imm> 1 VEXT{<c>}{<q>}.8 {<Qd>, }<Qn>, <Qm>, #<imm> if Q == '1' && (Vd[0] == '1' || Vn[0] == '1' || Vm[0] == '1') then Undefined(); end; if Q == '0' && imm4[3] == '1' then Undefined(); end; let quadword_operation : boolean = (Q == '1'); let position : integer{} = 8 * UInt(imm4); let d : integer = UInt(D::Vd); let n : integer = UInt(N::Vn); let m : integer = UInt(M::Vm); <c> For the "A1 128-bit SIMD vector" and "A1 64-bit SIMD vector" variants: see Standard assembler syntax fields. This encoding must be unconditional. <c> For the "T1 128-bit SIMD vector" and "T1 64-bit SIMD vector" variants: see Standard assembler syntax fields. <q> See Standard assembler syntax fields. <Dd> Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field. <Dn> Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field. <Dm> Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field. <imm> For the "A1 64-bit SIMD vector" and "T1 64-bit SIMD vector" variants: is the location of the extracted result in the concatenation of the operands, as a number of bytes from the least significant end, in the range 0 to 7, encoded in the "imm4" field. <imm> For the "A1 128-bit SIMD vector" and "T1 128-bit SIMD vector" variants: is the location of the extracted result in the concatenation of the operands, as a number of bytes from the least significant end, in the range 0 to 15, encoded in the "imm4" field. <Qd> Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2. <Qn> Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2. <Qm> Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2. Alias Conditions if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDEnabled(); if quadword_operation then Q(d>>1) = (Q(m>>1)::Q(n>>1))[position+127:position]; else D(d) = (D(m)::D(n))[position+63:position]; end; end; 2026-03-26 20:27:25 2026-03_rel