<?xml version="1.0" ?><?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?><!DOCTYPE instructionsection  PUBLIC '-//ARM//DTD instructionsection //EN'  'iform-p.dtd'><!-- Copyright (c) 2010-2026 Arm Limited or its affiliates. All rights reserved. --><!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. --><instructionsection id="VFMA_bf" title="VFMAB, VFMAT (BFloat16, vector) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd"/>
    <docvar key="mnemonic" value="VFMA"/>
    <docvar key="simdvectorsize" value="quad"/>
  </docvars>
  <heading>VFMAB, VFMAT (BFloat16, vector)</heading>
  <desc>
    <brief>
      <para>BFloat16 floating-point widening multiply-add long (vector)</para>
    </brief>
    <authored>
      <para>The Bfloat16 floating-point widening multiply-add long instruction widens the even-numbered (bottom)
or odd-numbered (top) 16-bit elements in the first and second source vectors from Bfloat16 to single-precision format. The instruction then multiplies
and adds these values to the overlapping single-precision elements of the destination vector.</para>
      <para>Unlike other BFloat16 multiplication instructions, this performs a fused multiply-add, without intermediate
rounding that uses the Round to Nearest rounding mode and can generate a floating-point exception that causes
cumulative exception bits in the <xref linkend="ARMARM_AArch32.fpscr">FPSCR</xref> to be set.</para>
    </authored>
  </desc>
  <alias_list howmany="0"/>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1"/>
        <docvar key="instr-class" value="fpsimd"/>
        <docvar key="isa" value="A32"/>
        <docvar key="mnemonic" value="VFMA"/>
        <docvar key="simdvectorsize" value="quad"/>
      </docvars>
      <iclassintro count="1"/>
      <arch_variants>
        <arch_variant feature="FEAT_AA32BF16" name="v8Ap6"/>
      </arch_variants>
      <regdiagram form="32" psname="A32.cops_as.advsimdext.simd3reg_sameext.VFMA_bf_A1_Q" tworows="1">
        <box hibit="31" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="27" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="25" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="24" width="2" name="op1" usename="1" settings="2" psbits="xx">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="1" name="D" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="21" width="2" name="op2" usename="1" settings="2" psbits="xx">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"/>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"/>
        </box>
        <box hibit="11" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="op3" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="9" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="op4" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="7" width="1" name="N" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="6" width="1" name="Q" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="5" width="1" name="M" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="4" name="U" usename="1" settings="1" psbits="x">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"/>
        </box>
      </regdiagram>
      <encoding name="VFMA_bf_A1_Q" oneofinclass="1" oneof="2" label="">
        <docvars>
          <docvar key="armarmheading" value="A1"/>
          <docvar key="instr-class" value="fpsimd"/>
          <docvar key="isa" value="A32"/>
          <docvar key="simdvectorsize" value="quad"/>
          <docvar key="mnemonic" value="VFMA"/>
        </docvars>
        <asmtemplate><text>VFMA</text><a hover="Is the bottom or top element specifier, " link="bt_option">&lt;bt&gt;</a><text>{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="qw_option">&lt;q&gt;</a><text>}.BF16  </text><a hover="Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the &quot;D:Vd&quot; field as &lt;Qd&gt;*2." link="D_Vd__4">&lt;Qd&gt;</a><text>, </text><a hover="Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the &quot;N:Vn&quot; field as &lt;Qn&gt;*2." link="N_Vn__2">&lt;Qn&gt;</a><text>, </text><a hover="Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the &quot;M:Vm&quot; field as &lt;Qm&gt;*2." link="M_Vm__5">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="A32.cops_as.advsimdext.simd3reg_sameext.VFMA_bf_A1_Q" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !IsFeatureImplemented(FEAT_AA32BF16) then Undefined(); end;
if Vd[0] == '1' || Vn[0] == '1' || Vm[0] == '1' then Undefined(); end;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
let elements : integer = 128 DIV 32;
let sel : integer = UInt(Q);</pstext></ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1"/>
        <docvar key="instr-class" value="fpsimd"/>
        <docvar key="isa" value="T32"/>
        <docvar key="mnemonic" value="VFMA"/>
        <docvar key="simdvectorsize" value="quad"/>
      </docvars>
      <iclassintro count="1"/>
      <arch_variants>
        <arch_variant feature="FEAT_AA32BF16" name="v8Ap6"/>
      </arch_variants>
      <regdiagram form="16x2" psname="T32.w.cpaf.advsimdext.simd_3sameext.VFMA_bf_T1_Q" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="27" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="25" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="24" width="2" name="op1" usename="1" settings="2" psbits="xx">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="1" name="D" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="21" width="2" name="op2" usename="1" settings="2" psbits="xx">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"/>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"/>
        </box>
        <box hibit="11" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="op3" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="9" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="op4" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="7" width="1" name="N" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="6" width="1" name="Q" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="5" width="1" name="M" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="4" name="U" usename="1" settings="1" psbits="x">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"/>
        </box>
      </regdiagram>
      <encoding name="VFMA_bf_T1_Q" oneofinclass="1" oneof="2" label="">
        <docvars>
          <docvar key="armarmheading" value="T1"/>
          <docvar key="instr-class" value="fpsimd"/>
          <docvar key="isa" value="T32"/>
          <docvar key="simdvectorsize" value="quad"/>
          <docvar key="mnemonic" value="VFMA"/>
        </docvars>
        <asmtemplate><text>VFMA</text><a hover="Is the bottom or top element specifier, " link="bt_option">&lt;bt&gt;</a><text>{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="qw_option">&lt;q&gt;</a><text>}.BF16  </text><a hover="Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the &quot;D:Vd&quot; field as &lt;Qd&gt;*2." link="D_Vd__4">&lt;Qd&gt;</a><text>, </text><a hover="Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the &quot;N:Vn&quot; field as &lt;Qn&gt;*2." link="N_Vn__2">&lt;Qn&gt;</a><text>, </text><a hover="Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the &quot;M:Vm&quot; field as &lt;Qm&gt;*2." link="M_Vm__5">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="T32.w.cpaf.advsimdext.simd_3sameext.VFMA_bf_T1_Q" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if <a link="func_InITBlock_0" file="shared_pseudocode.xml">InITBlock</a>() then UnpredictableProcedure(); end;
if !IsFeatureImplemented(FEAT_AA32BF16) then Undefined(); end;
if Vd[0] == '1' || Vn[0] == '1' || Vm[0] == '1' then Undefined(); end;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
let elements : integer = 128 DIV 32;
let sel : integer = UInt(Q);</pstext></ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VFMA_bf_A1_Q, VFMA_bf_T1_Q" symboldefcount="1">
      <symbol link="bt_option">&lt;bt&gt;</symbol>
      <definition encodedin="Q">
        <intro>Is the bottom or top element specifier, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">Q</entry>
                <entry class="symbol">&lt;bt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">B</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">T</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VFMA_bf_A1_Q, VFMA_bf_T1_Q" symboldefcount="1">
      <symbol link="qw_option">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMA_bf_A1_Q, VFMA_bf_T1_Q" symboldefcount="1">
      <symbol link="D_Vd__4">&lt;Qd&gt;</symbol>
      <account encodedin="(D :: Vd)">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the &quot;D:Vd&quot; field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMA_bf_A1_Q, VFMA_bf_T1_Q" symboldefcount="1">
      <symbol link="N_Vn__2">&lt;Qn&gt;</symbol>
      <account encodedin="(N :: Vn)">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the &quot;N:Vn&quot; field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMA_bf_A1_Q, VFMA_bf_T1_Q" symboldefcount="1">
      <symbol link="M_Vm__5">&lt;Qm&gt;</symbol>
      <account encodedin="(M :: Vm)">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the &quot;M:Vm&quot; field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="A32.cops_as.advsimdext.simd3reg_sameext.VFMA_bf_A1_Q" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="func_CheckAdvSIMDEnabled_0" file="shared_pseudocode.xml">CheckAdvSIMDEnabled</a>();
let fpcr : FPCR_Type = <a link="func_StandardFPCR_0" file="shared_pseudocode.xml">StandardFPCR</a>();

let operand1 : bits(128) = <a link="accessor_Q_1" file="shared_pseudocode.xml">Q</a>(n&gt;&gt;1);
let operand2 : bits(128) = <a link="accessor_Q_1" file="shared_pseudocode.xml">Q</a>(m&gt;&gt;1);
let operand3 : bits(128) = <a link="accessor_Q_1" file="shared_pseudocode.xml">Q</a>(d&gt;&gt;1);
var result : bits(128);

for e = 0 to elements-1 do
    let element1 : bits(32) = operand1[(2 * e + sel)*:16] :: Zeros{16};
    let element2 : bits(32) = operand2[(2 * e + sel)*:16] :: Zeros{16};
    let addend : bits(32) = operand3[e*:32];
    result[e*:32] = <a link="func_FPMulAdd_5" file="shared_pseudocode.xml">FPMulAdd</a>{32}(addend, element1, element2, fpcr);
end;

<a link="accessor_Q_1" file="shared_pseudocode.xml">Q</a>(d&gt;&gt;1) = result;</pstext></ps>
  </ps_section>
  <timestamp>2026-03-26 20:27:25</timestamp>
  <commit_id>2026-03_rel</commit_id>
</instructionsection>