VFMAL (by scalar)
Vector Floating-point Multiply-Add Long to accumulator (by scalar)
Vector Floating-point Multiply-Add Long to accumulator (by scalar).
This instruction multiplies the vector elements in the first source
SIMD&FP register by the specified value in the second source SIMD&FP
register, and accumulates the product to the corresponding
vector element of the destination SIMD&FP register.
The instruction does not round the result of the multiply before the
accumulation.
Depending on settings in the CPACR,
NSACR,
HCPTR, and
FPEXC registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information see Enabling Advanced
SIMD and floating-point support.
In Armv8.2 and Armv8.3, this is an OPTIONAL instruction.
From Armv8.4 it is mandatory for all implementations to support it.
ID_ISAR6.FHM indicates whether this instruction is supported.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
1
1
1
1
1
1
1
0
0
0
0
1
0
0
0
1
0
VFMAL{<q>}.F16 <Dd>, <Sn>, <Sm>[<index>]
1
VFMAL{<q>}.F16 <Qd>, <Dn>, <Dm>[<index>]
if !IsFeatureImplemented(FEAT_FHM) then Undefined(); end;
if Q == '1' && Vd[0] == '1' then Undefined(); end;
let d : integer = UInt(D::Vd);
let n : integer = if Q == '1' then UInt(N::Vn) else UInt(Vn::N);
let m : integer = if Q == '1' then UInt(Vm[2:0]) else UInt(Vm[2:0]::M);
let index : integer = if Q == '1' then UInt(M::Vm[3]) else UInt(Vm[3]);
let esize : integer{} = 32;
let datasize : integer{} = 32 << UInt(Q);
let sub_op : boolean = S == '1';
let regs : integer = if Q == '0' then 1 else 2;
1
1
1
1
1
1
1
0
0
0
0
1
0
0
0
1
0
VFMAL{<q>}.F16 <Dd>, <Sn>, <Sm>[<index>]
1
VFMAL{<q>}.F16 <Qd>, <Dn>, <Dm>[<index>]
if InITBlock() then UnpredictableProcedure(); end;
if !IsFeatureImplemented(FEAT_FHM) then Undefined(); end;
if Q == '1' && Vd[0] == '1' then Undefined(); end;
let d : integer = UInt(D::Vd);
let n : integer = if Q == '1' then UInt(N::Vn) else UInt(Vn::N);
let m : integer = if Q == '1' then UInt(Vm[2:0]) else UInt(Vm[2:0]::M);
let index : integer = if Q == '1' then UInt(M::Vm[3]) else UInt(Vm[3]);
let esize : integer{} = 32;
let datasize : integer{} = 32 << UInt(Q);
let sub_op : boolean = S == '1';
let regs : integer = if Q == '0' then 1 else 2;
<q>
See Standard assembler syntax fields.
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
<Sn>
Is the 32-bit name of the first SIMD&FP source register, encoded in the "Vn:N" field.
<Sm>
Is the 32-bit name of the second SIMD&FP source register, encoded in the "Vm<2:0>:M" field.
<index>
For the "A1 64-bit SIMD vector" and "T1 64-bit SIMD vector" variants: is the element index in the range 0 to 1, encoded in the "Vm<3>" field.
<index>
For the "A1 128-bit SIMD vector" and "T1 128-bit SIMD vector" variants: is the element index in the range 0 to 3, encoded in the "M:Vm<3>" field.
<Qd>
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.
<Dn>
Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.
<Dm>
Is the 64-bit name of the second SIMD&FP source register, encoded in the "Vm<2:0>" field.
CheckAdvSIMDEnabled();
var operand1 : bits(datasize) ;
var operand2 : bits(datasize) ;
var operand3 : bits(64);
var result : bits(64);
var element1 : bits(esize DIV 2);
var element2 : bits(esize DIV 2);
let fpcr : FPCR_Type = StandardFPCR();
if Q=='0' then
operand1 = S(n)[datasize-1:0];
operand2 = S(m)[datasize-1:0];
else
operand1 = D(n)[datasize-1:0];
operand2 = D(m)[datasize-1:0];
end;
element2 = operand2[index*:(esize DIV 2)];
for r = 0 to regs-1 do
operand3 = D(d+r);
for e = 0 to 1 do
element1 = operand1[(2*r+e)*:(esize DIV 2)];
if sub_op then element1 = FPNeg{esize DIV 2}(element1, fpcr); end;
result[e*:esize] = FPMulAddH(operand3[e*:esize], element1, element2, fpcr);
end;
D(d+r) = result;
end;
2026-03-26 20:27:25
2026-03_rel