VHADD
Vector Halving Add
Vector Halving Add adds corresponding elements in two vectors of
integers, shifts each result right one bit, and places the final
results in the destination vector. The results of the halving
operations are truncated. For rounded results, see
VRHADD).
The operand and result elements are all the same type, and can be
any one of:
8-bit, 16-bit, or 32-bit signed integers.
8-bit, 16-bit, or 32-bit unsigned integers.
Depending on settings in the CPACR,
NSACR, and
HCPTR registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information see Enabling Advanced
SIMD and floating-point support.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
1
1
1
1
0
0
1
0
0
0
0
0
0
0
VHADD{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>
1
VHADD{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>
if Q == '1' && (Vd[0] == '1' || Vn[0] == '1' || Vm[0] == '1') then Undefined(); end;
if size == '11' then Undefined(); end;
let add : boolean = (op == '0');
let unsigned : boolean = (U == '1');
let esize : integer{} = 8 << UInt(size);
let elements : integer{} = 64 DIV esize;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
let regs : integer = if Q == '0' then 1 else 2;
1
1
1
1
1
1
1
0
0
0
0
0
0
0
VHADD{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>
1
VHADD{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>
if Q == '1' && (Vd[0] == '1' || Vn[0] == '1' || Vm[0] == '1') then Undefined(); end;
if size == '11' then Undefined(); end;
let add : boolean = (op == '0');
let unsigned : boolean = (U == '1');
let esize : integer{} = 8 << UInt(size);
let elements : integer{} = 64 DIV esize;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
let regs : integer = if Q == '0' then 1 else 2;
<c>
For the "A1 128-bit SIMD vector" and "A1 64-bit SIMD vector" variants: see Standard assembler syntax fields. This encoding must be unconditional.
<c>
For the "T1 128-bit SIMD vector" and "T1 64-bit SIMD vector" variants: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<dt>
Is the data type for the elements of the operands,
U
size
<dt>
0
00
S8
0
01
S16
0
10
S32
1
00
U8
1
01
U16
1
10
U32
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
<Dn>
Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.
<Dm>
Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.
<Qd>
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.
<Qn>
Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.
<Qm>
Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.
if ConditionPassed() then
EncodingSpecificOperations();
CheckAdvSIMDEnabled();
for r = 0 to regs-1 do
for e = 0 to elements-1 do
let op1elt : bits(esize) = D(n+r)[e*:esize];
let op2elt : bits(esize) = D(m+r)[e*:esize];
let element1 : integer = if unsigned then UInt(op1elt) else SInt(op1elt);
let element2 : integer = if unsigned then UInt(op2elt) else SInt(op2elt);
let result : integer = (if add then element1+element2 else element1-element2) >> 1;
D(d+r)[e*:esize] = result[esize-1:0];
end;
end;
end;
2026-03-26 20:27:25
2026-03_rel