VJCVT
JavaScript Convert to signed fixed-point, rounding toward Zero
JavaScript Convert to signed fixed-point, rounding toward Zero.
This instruction converts the double-precision floating-point value
in the SIMD&FP source register to a 32-bit signed integer using
the Round towards Zero rounding mode, and writes the result to the
SIMD&FP destination register.
If the result is too large to be accommodated as a signed 32-bit
integer, then the result is the integer modulo 232, as held in
a 32-bit signed integer.
This instruction can generate a floating-point exception.
Depending on the settings in FPSCR,
the exception results in either a flag being set
or a synchronous exception being generated.
For more information, see
Floating-point exceptions and exception traps.
Depending on settings in the CPACR,
NSACR,
HCPTR, and
FPEXC registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information see Enabling Advanced
SIMD and floating-point support.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
!= 1111
1
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0
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0
0
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0
VJCVT{<q>}.S32.F64 <Sd>, <Dm>
if !IsFeatureImplemented(FEAT_JSCVT) then Undefined(); end;
if cond != '1110' then UnpredictableProcedure(); end;
let d : integer = UInt(Vd::D);
let m : integer = UInt(M::Vm);
1
1
1
0
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VJCVT{<q>}.S32.F64 <Sd>, <Dm>
if !IsFeatureImplemented(FEAT_JSCVT) then Undefined(); end;
if InITBlock() then UnpredictableProcedure(); end;
let d : integer = UInt(Vd::D);
let m : integer = UInt(M::Vm);
<q>
See Standard assembler syntax fields.
<Sd>
Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.
<Dm>
Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.
EncodingSpecificOperations();
CheckVFPEnabled(TRUE);
let fltval : bits(64) = D(m);
var intval : bits(32);
var Z : bit;
(intval, Z) = FPToFixedJS(fltval, EffectiveFPCR());
FPSCR()[31:28] = '0'::Z::'00';
S(d) = intval;
2026-03-26 20:27:25
2026-03_rel