VMMLA
BFloat16 floating-point matrix multiply-accumulate
BFloat16 floating-point matrix multiply-accumulate.
This instruction multiplies the 2x4 matrix of BF16 values
in the first 128-bit source vector by the 4x2 BF16 matrix
in the second 128-bit source vector. The resulting 2x2
single-precision matrix product is then added destructively
to the 2x2 single-precision matrix in the 128-bit destination
vector. This is equivalent to performing a 4-way dot product
per destination element. The instruction does not update the FPSCR exception status.
Arm expects that the VMMLA instruction will deliver a
peak BF16 multiply throughput that is at least as high as
can be achieved using two VDOT instructions, with a goal
that it should have significantly higher throughput.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
1
1
1
1
1
1
0
0
0
0
0
1
1
0
0
1
0
VMMLA{<q>}.BF16 <Qd>, <Qn>, <Qm>
if !IsFeatureImplemented(FEAT_AA32BF16) then Undefined(); end;
if Vd[0] == '1' || Vn[0] == '1' || Vm[0] == '1' then Undefined(); end;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
let regs : integer = 2;
1
1
1
1
1
1
0
0
0
0
0
1
1
0
0
1
0
VMMLA{<q>}.BF16 <Qd>, <Qn>, <Qm>
if InITBlock() then UnpredictableProcedure(); end;
if !IsFeatureImplemented(FEAT_AA32BF16) then Undefined(); end;
if Vd[0] == '1' || Vn[0] == '1' || Vm[0] == '1' then Undefined(); end;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
let regs : integer = 2;
<q>
See Standard assembler syntax fields.
<Qd>
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.
<Qn>
Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.
<Qm>
Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.
CheckAdvSIMDEnabled();
let operand1 : bits(128) = Q(n>>1);
let operand2 : bits(128) = Q(m>>1);
let acc : bits(128) = Q(d>>1);
let fpcr : FPCR_Type = EffectiveFPCR();
Q(d>>1) = BFMatMulAddH(acc, operand1, operand2, fpcr);
2026-03-26 20:27:25
2026-03_rel