VMOV (immediate)
Copy immediate value to a SIMD&FP register
Copy immediate value to a SIMD&FP register places an immediate
constant into every element of the destination register.
Depending on settings in the CPACR,
NSACR,
HCPTR, and
FPEXC registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode. For more information see
Enabling Advanced SIMD and floating-point
support.
Related encodings: See Advanced SIMD one register and modified immediate for the T32 instruction set, or Advanced SIMD one register and modified immediate for the A32 instruction set.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
,
A2
,
A3
,
A4
and
A5
)
and
T32 (
T1
,
T2
,
T3
,
T4
and
T5
)
.
1
1
1
1
0
0
1
1
0
0
0
0
x
x
0
0
0
1
0
VMOV{<c>}{<q>}.I32 <Dd>, #<imm>
1
VMOV{<c>}{<q>}.I32 <Qd>, #<imm>
if op == '0' && cmode[0] == '1' && cmode[3:2] != '11' then See("VORR (immediate)"); end;
if op == '1' && cmode != '1110' then See("Related encodings"); end;
if Q == '1' && Vd[0] == '1' then Undefined(); end;
let advsimd : boolean = TRUE;
let esize : integer{} = 64;
let imm : bits(esize) = AdvSIMDExpandImm(op, cmode, i::imm3::imm4);
let d : integer = UInt(D::Vd);
let regs : integer = if Q == '0' then 1 else 2;
!= 1111
1
1
1
0
1
1
1
1
0
(0)
0
(0)
0
0
1
VMOV{<c>}{<q>}.F16 <Sd>, #<imm>
1
0
VMOV{<c>}{<q>}.F32 <Sd>, #<imm>
1
1
VMOV{<c>}{<q>}.F64 <Dd>, #<imm>
if FPSCR().Len != '000' || FPSCR().Stride != '00' then Undefined(); end;
if size == '00' || (size == '01' && !IsFeatureImplemented(FEAT_FP16)) then Undefined(); end;
if size == '01' && cond != '1110' then UnpredictableProcedure(); end;
let esize : integer{} = 8 << UInt(size);
let imm : bits(esize) = VFPExpandImm{}(imm4H::imm4L);
let advsimd : boolean = FALSE;
let d : integer = if size == '11' then UInt(D::Vd) else UInt(Vd::D);
let regs : integer = if size == '11' then 1 else 0;
size == '01' && cond != '1110'
The instruction executes as if it passes the Condition code check.
The instruction executes as NOP. This means it behaves as if it fails the Condition code check.
1
1
1
1
0
0
1
1
0
0
0
1
0
x
0
0
0
1
0
VMOV{<c>}{<q>}.I16 <Dd>, #<imm>
1
VMOV{<c>}{<q>}.I16 <Qd>, #<imm>
if op == '0' && cmode[0] == '1' && cmode[3:2] != '11' then See("VORR (immediate)"); end;
if op == '1' && cmode != '1110' then See("Related encodings"); end;
if Q == '1' && Vd[0] == '1' then Undefined(); end;
let advsimd : boolean = TRUE;
let esize : integer{} = 64;
let imm : bits(esize) = AdvSIMDExpandImm(op, cmode, i::imm3::imm4);
let d : integer = UInt(D::Vd);
let regs : integer = if Q == '0' then 1 else 2;
1
1
1
1
0
0
1
1
0
0
0
1
1
x
x
0
0
1
0
VMOV{<c>}{<q>}.<dt> <Dd>, #<imm>
1
VMOV{<c>}{<q>}.<dt> <Qd>, #<imm>
if op == '0' && cmode[0] == '1' && cmode[3:2] != '11' then See("VORR (immediate)"); end;
if op == '1' && cmode != '1110' then See("Related encodings"); end;
if Q == '1' && Vd[0] == '1' then Undefined(); end;
let advsimd : boolean = TRUE;
let esize : integer{} = 64;
let imm : bits(esize) = AdvSIMDExpandImm(op, cmode, i::imm3::imm4);
let d : integer = UInt(D::Vd);
let regs : integer = if Q == '0' then 1 else 2;
1
1
1
1
0
0
1
1
0
0
0
1
1
1
0
0
1
1
0
VMOV{<c>}{<q>}.I64 <Dd>, #<imm>
1
VMOV{<c>}{<q>}.I64 <Qd>, #<imm>
if op == '0' && cmode[0] == '1' && cmode[3:2] != '11' then See("VORR (immediate)"); end;
if op == '1' && cmode != '1110' then See("Related encodings"); end;
if Q == '1' && Vd[0] == '1' then Undefined(); end;
let advsimd : boolean = TRUE;
let esize : integer{} = 64;
let imm : bits(esize) = AdvSIMDExpandImm(op, cmode, i::imm3::imm4);
let d : integer = UInt(D::Vd);
let regs : integer = if Q == '0' then 1 else 2;
1
1
1
1
1
1
1
1
0
0
0
0
x
x
0
0
0
1
0
VMOV{<c>}{<q>}.I32 <Dd>, #<imm>
1
VMOV{<c>}{<q>}.I32 <Qd>, #<imm>
if op == '0' && cmode[0] == '1' && cmode[3:2] != '11' then See("VORR (immediate)"); end;
if op == '1' && cmode != '1110' then See("Related encodings"); end;
if Q == '1' && Vd[0] == '1' then Undefined(); end;
let advsimd : boolean = TRUE;
let esize : integer{} = 64;
let imm : bits(esize) = AdvSIMDExpandImm(op, cmode, i::imm3::imm4);
let d : integer = UInt(D::Vd);
let regs : integer = if Q == '0' then 1 else 2;
1
1
1
0
1
1
1
0
1
1
1
1
0
(0)
0
(0)
0
0
1
VMOV{<c>}{<q>}.F16 <Sd>, #<imm>
1
0
VMOV{<c>}{<q>}.F32 <Sd>, #<imm>
1
1
VMOV{<c>}{<q>}.F64 <Dd>, #<imm>
if FPSCR().Len != '000' || FPSCR().Stride != '00' then Undefined(); end;
if size == '00' || (size == '01' && !IsFeatureImplemented(FEAT_FP16)) then Undefined(); end;
if size == '01' && InITBlock() then UnpredictableProcedure(); end;
let esize : integer{} = 8 << UInt(size);
let imm : bits(esize) = VFPExpandImm{}(imm4H::imm4L);
let advsimd : boolean = FALSE;
let d : integer = if size == '11' then UInt(D::Vd) else UInt(Vd::D);
let regs : integer = if size == '11' then 1 else 0;
size == '01' && InITBlock()
The instruction executes as if it passes the Condition code check.
The instruction executes as NOP. This means it behaves as if it fails the Condition code check.
1
1
1
1
1
1
1
1
0
0
0
1
0
x
0
0
0
1
0
VMOV{<c>}{<q>}.I16 <Dd>, #<imm>
1
VMOV{<c>}{<q>}.I16 <Qd>, #<imm>
if op == '0' && cmode[0] == '1' && cmode[3:2] != '11' then See("VORR (immediate)"); end;
if op == '1' && cmode != '1110' then See("Related encodings"); end;
if Q == '1' && Vd[0] == '1' then Undefined(); end;
let advsimd : boolean = TRUE;
let esize : integer{} = 64;
let imm : bits(esize) = AdvSIMDExpandImm(op, cmode, i::imm3::imm4);
let d : integer = UInt(D::Vd);
let regs : integer = if Q == '0' then 1 else 2;
1
1
1
1
1
1
1
1
0
0
0
1
1
x
x
0
0
1
0
VMOV{<c>}{<q>}.<dt> <Dd>, #<imm>
1
VMOV{<c>}{<q>}.<dt> <Qd>, #<imm>
if op == '0' && cmode[0] == '1' && cmode[3:2] != '11' then See("VORR (immediate)"); end;
if op == '1' && cmode != '1110' then See("Related encodings"); end;
if Q == '1' && Vd[0] == '1' then Undefined(); end;
let advsimd : boolean = TRUE;
let esize : integer{} = 64;
let imm : bits(esize) = AdvSIMDExpandImm(op, cmode, i::imm3::imm4);
let d : integer = UInt(D::Vd);
let regs : integer = if Q == '0' then 1 else 2;
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
0
1
1
0
VMOV{<c>}{<q>}.I64 <Dd>, #<imm>
1
VMOV{<c>}{<q>}.I64 <Qd>, #<imm>
if op == '0' && cmode[0] == '1' && cmode[3:2] != '11' then See("VORR (immediate)"); end;
if op == '1' && cmode != '1110' then See("Related encodings"); end;
if Q == '1' && Vd[0] == '1' then Undefined(); end;
let advsimd : boolean = TRUE;
let esize : integer{} = 64;
let imm : bits(esize) = AdvSIMDExpandImm(op, cmode, i::imm3::imm4);
let d : integer = UInt(D::Vd);
let regs : integer = if Q == '0' then 1 else 2;
<c>
For the "A1 128-bit SIMD vector", "A1 64-bit SIMD vector", "A3 128-bit SIMD vector", "A3 64-bit SIMD vector", "A4 128-bit SIMD vector", "A4 64-bit SIMD vector", "A5 128-bit SIMD vector", and "A5 64-bit SIMD vector" variants: see Standard assembler syntax fields. This encoding must be unconditional.
<c>
For the "A2 Double-precision scalar", "A2 Half-precision scalar", and "A2 Single-precision scalar" variants: see Standard assembler syntax fields.
<c>
For the "T1 128-bit SIMD vector", "T1 64-bit SIMD vector", "T2 Double-precision scalar", "T2 Half-precision scalar", "T2 Single-precision scalar", "T3 128-bit SIMD vector", "T3 64-bit SIMD vector", "T4 128-bit SIMD vector", "T4 64-bit SIMD vector", "T5 128-bit SIMD vector", and "T5 64-bit SIMD vector" variants: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
<imm>
For the "A1 128-bit SIMD vector", "A1 64-bit SIMD vector", "A3 128-bit SIMD vector", "A3 64-bit SIMD vector", "A4 128-bit SIMD vector", "A4 64-bit SIMD vector", "A5 128-bit SIMD vector", "A5 64-bit SIMD vector", "T1 128-bit SIMD vector", "T1 64-bit SIMD vector", "T3 128-bit SIMD vector", "T3 64-bit SIMD vector", "T4 128-bit SIMD vector", "T4 64-bit SIMD vector", "T5 128-bit SIMD vector", and "T5 64-bit SIMD vector" variants: is a constant of the specified type that is replicated to fill the destination register. For details of the range of constants available and the encoding of <imm>, see Modified immediate constants in T32 and A32 Advanced SIMD instructions.
<imm>
For the "A2 Double-precision scalar", "A2 Half-precision scalar", "A2 Single-precision scalar", "T2 Double-precision scalar", "T2 Half-precision scalar", and "T2 Single-precision scalar" variants: is a signed floating-point constant with 3-bit exponent and normalized 4 bits of precision, encoded in "imm4H:imm4L". For details of the range of constants available and the encoding of <imm>, see Modified immediate constants in T32 and A32 floating-point instructions.
<Qd>
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.
<Sd>
Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.
<dt>
The data type,
cmode
<dt>
110x
I32
1110
I8
1111
F32
if ConditionPassed() then
EncodingSpecificOperations();
CheckAdvSIMDOrVFPEnabled(TRUE, advsimd);
if esize <= 32 then
S(d) = ZeroExtend{32}(imm);
else
for r = 0 to regs-1 do
D(d+r) = ZeroExtend{64}(imm);
end;
end;
end;
2026-03-26 20:27:25
2026-03_rel