VMOV (between general-purpose register and single-precision) Copy a general-purpose register to or from a 32-bit SIMD&FP register Copy a general-purpose register to or from a 32-bit SIMD&FP register. This instruction transfers the value held in a 32-bit SIMD&FP register to a general-purpose register, or the value held in a general-purpose register to a 32-bit SIMD&FP register. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support. For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors. This instruction is a data-independent-time instruction as described in About the DIT bit. It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) . != 1111 1 1 1 0 0 0 0 1 0 1 0 (0) (0) 1 (0) (0) (0) (0) 0 VMOV{<c>}{<q>} <Sn>, <Rt> 1 VMOV{<c>}{<q>} <Rt>, <Sn> let to_arm_register : boolean = (op == '1'); let t : integer = UInt(Rt); let n : integer = UInt(Vn::N); // Armv8-A removes UNPREDICTABLE for R13 if t == 15 then UnpredictableProcedure(); end; 1 1 1 0 1 1 1 0 0 0 0 1 0 1 0 (0) (0) 1 (0) (0) (0) (0) 0 VMOV{<c>}{<q>} <Sn>, <Rt> 1 VMOV{<c>}{<q>} <Rt>, <Sn> let to_arm_register : boolean = (op == '1'); let t : integer = UInt(Rt); let n : integer = UInt(Vn::N); // Armv8-A removes UNPREDICTABLE for R13 if t == 15 then UnpredictableProcedure(); end; <c> See Standard assembler syntax fields. <q> See Standard assembler syntax fields. <Sn> Is the 32-bit name of the SIMD&FP register to be transferred, encoded in the "Vn:N" field. <Rt> Is the general-purpose register that <Sn> will be transferred to or from, encoded in the "Rt" field. if ConditionPassed() then EncodingSpecificOperations(); CheckVFPEnabled(TRUE); if to_arm_register then R(t) = S(n); else S(n) = R(t); end; end; 2026-03-26 20:27:25 2026-03_rel