VMULL (integer and polynomial)
Vector Multiply Long (integer and polynomial)
Vector Multiply Long multiplies corresponding elements in two vectors.
The destination vector elements are twice as long as the elements
that are multiplied.
For information about multiplying polynomials see
Polynomial arithmetic over {0, 1}.
Depending on settings in the CPACR,
NSACR, and
HCPTR registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information see Enabling Advanced
SIMD and floating-point support.
For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
Related encodings: See Advanced SIMD data-processing for the T32 instruction set, or Advanced SIMD data-processing for the A32 instruction set.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
1
1
1
1
0
0
1
1
!= 11
1
1
0
0
0
VMULL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm>
if size == '11' then See("Related encodings"); end;
if op == '1' && (U == '1' || size == '01') then Undefined(); end;
if op == '1' && size =='10' && !IsFeatureImplemented(FEAT_PMULL) then Undefined(); end;
if Vd[0] == '1' then Undefined(); end;
let unsigned : boolean = (U == '1');
let polynomial : boolean = (op == '1');
let long_destination : boolean = TRUE;
let esize : integer{} = if polynomial && size == '10' then 64 else 8 << UInt(size);
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
let elements : integer = 64 DIV esize;
let regs : integer = 1;
1
1
1
1
1
1
1
1
!= 11
1
1
0
0
0
VMULL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm>
if size == '11' then See("Related encodings"); end;
if op == '1' && (U == '1' || size == '01') then Undefined(); end;
if op == '1' && size == '10' && InITBlock() then UnpredictableProcedure(); end;
if op == '1' && size == '10' && !IsFeatureImplemented(FEAT_PMULL) then
UnpredictableProcedure();
end;
if Vd[0] == '1' then Undefined(); end;
let unsigned : boolean = (U == '1');
let polynomial : boolean = (op == '1');
let long_destination : boolean = TRUE;
let esize : integer{} = if polynomial && size == '10' then 64 else 8 << UInt(size);
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
let elements : integer = 64 DIV esize;
let regs : integer = 1;
op == '1' && size == '10' && InITBlock()
The instruction executes as if it passes the Condition code check.
The instruction executes as NOP. This means it behaves as if it fails the Condition code check.
<c>
For the "A1" variant: see Standard assembler syntax fields. This encoding must be unconditional.
<c>
For the "T1" variant: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<dt>
Is the data type for the elements of the operands,
op
U
size
<dt>
0
0
00
S8
0
0
01
S16
0
0
10
S32
0
1
00
U8
0
1
01
U16
0
1
10
U32
1
0
00
P8
1
0
10
P64
<Qd>
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.
<Dn>
Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.
<Dm>
Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.
if ConditionPassed() then
EncodingSpecificOperations();
CheckAdvSIMDEnabled();
for r = 0 to regs-1 do
for e = 0 to elements-1 do
let op1elt : bits(esize) = Din(n+r)[e*:esize];
let op2elt : bits(esize) = Din(m+r)[e*:esize];
var product : bits(2 * esize);
if polynomial then
product = PolynomialMult{esize, esize}(op1elt, op2elt);
else
let element1 : integer = if unsigned then UInt(op1elt) else SInt(op1elt);
let element2 : integer = if unsigned then UInt(op2elt) else SInt(op2elt);
product = (element1 * element2)[2*esize-1:0];
end;
if long_destination then
Q(d>>1)[e*:(2*esize)] = product;
else
D(d+r)[e*:esize] = product[esize-1:0];
end;
end;
end;
end;
2026-03-26 20:27:25
2026-03_rel