VQSHL, VQSHLU (immediate)
Vector Saturating Shift Left (immediate)
Vector Saturating Shift Left (immediate) takes each element
in a vector of integers, left shifts them by an immediate value,
and places the results in a second vector.
The operand elements must all be the same size, and can be
any one of:
8-bit, 16-bit, 32-bit, or 64-bit signed integers.
8-bit, 16-bit, 32-bit, or 64-bit unsigned integers.
The result elements are the same size as the operand elements.
If the operand elements are signed, the results can be either signed
or unsigned. If the operand elements are unsigned, the result elements
must also be unsigned.
If any of the results overflow, they are saturated. The cumulative
saturation bit, FPSCR.QC, is set if
saturation occurs. For details see Pseudocode
details of saturation.
Depending on settings in the CPACR,
NSACR, and
HCPTR registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information see Enabling Advanced
SIMD and floating-point support.
Related encodings: See Advanced SIMD one register and modified immediate for the T32 instruction set, or Advanced SIMD one register and modified immediate for the A32 instruction set.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
1
1
1
1
0
0
1
1
0
1
1
1
1
0
VQSHL{<c>}{<q>}.<type><size> {<Dd>, }<Dm>, #<imm>
1
0
0
VQSHLU{<c>}{<q>}.<type><size> {<Dd>, }<Dm>, #<imm>
1
1
VQSHL{<c>}{<q>}.<type><size> {<Qd>, }<Qm>, #<imm>
1
0
1
VQSHLU{<c>}{<q>}.<type><size> {<Qd>, }<Qm>, #<imm>
if (L::imm6) == '0000xxx' then See("Related encodings"); end;
if U == '0' && op == '0' then Undefined(); end;
if Q == '1' && (Vd[0] == '1' || Vm[0] == '1') then Undefined(); end;
let esize : integer{} = 8 << HighestSetBitNZ((L::imm6)[6:3]);
let elements : integer = 64 DIV esize;
let shift_amount : integer = UInt(L::imm6) - esize;
let src_unsigned : boolean = (U == '1' && op == '1');
let dest_unsigned : boolean = (U == '1');
let d : integer = UInt(D::Vd);
let m : integer = UInt(M::Vm);
let regs : integer = if Q == '0' then 1 else 2;
1
1
1
1
1
1
1
1
0
1
1
1
1
0
VQSHL{<c>}{<q>}.<type><size> {<Dd>, }<Dm>, #<imm>
1
0
0
VQSHLU{<c>}{<q>}.<type><size> {<Dd>, }<Dm>, #<imm>
1
1
VQSHL{<c>}{<q>}.<type><size> {<Qd>, }<Qm>, #<imm>
1
0
1
VQSHLU{<c>}{<q>}.<type><size> {<Qd>, }<Qm>, #<imm>
if (L::imm6) == '0000xxx' then See("Related encodings"); end;
if U == '0' && op == '0' then Undefined(); end;
if Q == '1' && (Vd[0] == '1' || Vm[0] == '1') then Undefined(); end;
let esize : integer{} = 8 << HighestSetBitNZ((L::imm6)[6:3]);
let elements : integer = 64 DIV esize;
let shift_amount : integer = UInt(L::imm6) - esize;
let src_unsigned : boolean = (U == '1' && op == '1');
let dest_unsigned : boolean = (U == '1');
let d : integer = UInt(D::Vd);
let m : integer = UInt(M::Vm);
let regs : integer = if Q == '0' then 1 else 2;
<c>
For the "A1 128-bit SIMD vector, signed result", "A1 128-bit SIMD vector, unsigned result", "A1 64-bit SIMD vector, signed result", and "A1 64-bit SIMD vector, unsigned result" variants: see Standard assembler syntax fields. This encoding must be unconditional.
<c>
For the "T1 128-bit SIMD vector, signed result", "T1 128-bit SIMD vector, unsigned result", "T1 64-bit SIMD vector, signed result", and "T1 64-bit SIMD vector, unsigned result" variants: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<type>
Is the data type for the elements of the vectors,
<size>
Is the data size for the elements of the vectors,
L
imm6
<size>
0
001xxx
8
0
01xxxx
16
0
1xxxxx
32
1
xxxxxx
64
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
<Dm>
Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.
<imm>
Is an immediate value, in the range 0 to <size>-1, encoded in the "imm6" field.
<Qd>
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.
<Qm>
Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.
if ConditionPassed() then
EncodingSpecificOperations();
CheckAdvSIMDEnabled();
for r = 0 to regs-1 do
for e = 0 to elements-1 do
let opelt : bits(esize) = D(m+r)[e*:esize];
let element : integer = if src_unsigned then UInt(opelt) else SInt(opelt);
let (result, sat) : (bits(esize), boolean) = SatQ{esize}(element << shift_amount,
dest_unsigned);
D(d+r)[e*:esize] = result;
if sat then FPSCR().QC = '1'; end;
end;
end;
end;
2026-03-26 20:27:25
2026-03_rel