VRINTX (floating-point)
Round floating-point to integer inexact
Round floating-point to integer inexact rounds a floating-point
value to an integral floating-point value of the same size, using
the rounding mode specified in the FPSCR, and raises an Inexact
exception when the result value is not numerically equal to the
input value. A zero input gives a zero result with the same sign, an
infinite input gives an infinite result with the same sign, and a
NaN is propagated as for normal arithmetic.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
!= 1111
1
1
1
0
1
1
1
0
1
1
1
1
0
0
1
0
0
1
VRINTX{<c>}{<q>}.F16 <Sd>, <Sm>
1
0
VRINTX{<c>}{<q>}.F32 <Sd>, <Sm>
1
1
VRINTX{<c>}{<q>}.F64 <Dd>, <Dm>
if size == '00' || (size == '01' && !IsFeatureImplemented(FEAT_FP16)) then Undefined(); end;
if size == '01' && cond != '1110' then UnpredictableProcedure(); end;
let exact : boolean = TRUE;
let esize : integer{} = 8 << UInt(size);
let d : integer = if size == '11' then UInt(D::Vd) else UInt(Vd::D);
let m : integer = if size == '11' then UInt(M::Vm) else UInt(Vm::M);
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
0
0
1
0
0
1
VRINTX{<c>}{<q>}.F16 <Sd>, <Sm>
1
0
VRINTX{<c>}{<q>}.F32 <Sd>, <Sm>
1
1
VRINTX{<c>}{<q>}.F64 <Dd>, <Dm>
if size == '00' || (size == '01' && !IsFeatureImplemented(FEAT_FP16)) then Undefined(); end;
if size == '01' && InITBlock() then UnpredictableProcedure(); end;
let exact : boolean = TRUE;
let esize : integer{} = 8 << UInt(size);
let d : integer = if size == '11' then UInt(D::Vd) else UInt(Vd::D);
let m : integer = if size == '11' then UInt(M::Vm) else UInt(Vm::M);
InITBlock()
The instruction executes as if it passes the Condition code check.
The instruction executes as NOP. This means it behaves as if it fails the Condition code check.
<c>
See Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Sd>
Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.
<Sm>
Is the 32-bit name of the SIMD&FP source register, encoded in the "Vm:M" field.
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
<Dm>
Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.
if ConditionPassed() then
EncodingSpecificOperations();
CheckVFPEnabled(TRUE);
let fpcr : FPCR_Type = EffectiveFPCR();
let rounding : FPRounding = FPRoundingMode(fpcr);
case esize of
when 16 =>
H(d) = FPRoundInt{16}(H(m), fpcr, rounding, exact);
when 32 =>
S(d) = FPRoundInt{32}(S(m), fpcr, rounding, exact);
when 64 =>
D(d) = FPRoundInt{64}(D(m), fpcr, rounding, exact);
end;
end;
2026-03-26 20:27:25
2026-03_rel