VRSUBHN
Vector Rounding Subtract and Narrow, returning High Half
Vector Rounding Subtract and Narrow, returning High Half subtracts
the elements of one quadword vector from the corresponding elements
of another quadword vector, takes the most significant half of each
result, and places the final results in a doubleword vector. The
results are rounded. For truncated results, see
VSUBHN.
The operand elements can be 16-bit, 32-bit, or 64-bit integers.
There is no distinction between signed and unsigned integers.
Depending on settings in the CPACR,
NSACR, and
HCPTR registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information see Enabling Advanced
SIMD and floating-point support.
Related encodings: See Advanced SIMD data-processing for the T32 instruction set, or Advanced SIMD data-processing for the A32 instruction set.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
1
1
1
1
0
0
1
1
1
!= 11
0
1
1
0
0
0
VRSUBHN{<c>}{<q>}.<dt> <Dd>, <Qn>, <Qm>
if size == '11' then See("Related encodings"); end;
if Vn[0] == '1' || Vm[0] == '1' then Undefined(); end;
let esize : integer{} = 8 << UInt(size);
let elements : integer = 64 DIV esize;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
1
1
1
1
1
1
1
1
1
!= 11
0
1
1
0
0
0
VRSUBHN{<c>}{<q>}.<dt> <Dd>, <Qn>, <Qm>
if size == '11' then See("Related encodings"); end;
if Vn[0] == '1' || Vm[0] == '1' then Undefined(); end;
let esize : integer{} = 8 << UInt(size);
let elements : integer = 64 DIV esize;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
<c>
For the "A1" variant: see Standard assembler syntax fields. This encoding must be unconditional.
<c>
For the "T1" variant: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<dt>
Is the data type for the elements of the operands,
size
<dt>
00
I16
01
I32
10
I64
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
<Qn>
Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.
<Qm>
Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.
if ConditionPassed() then
EncodingSpecificOperations();
CheckAdvSIMDEnabled();
let round : boolean = TRUE;
for e = 0 to elements-1 do
let result : integer = (RShr(UInt(Qin(n>>1)[e*:(2*esize)] -
Qin(m>>1)[e*:(2*esize)]), esize, round));
D(d)[e*:esize] = result[esize-1:0];
end;
end;
2026-03-26 20:27:25
2026-03_rel