VSDOT (vector)
Dot Product vector form with signed integers
Dot Product vector form with signed integers. This instruction performs the
dot product of the four 8-bit elements in each 32-bit element of the first
source register with the four 8-bit elements of the corresponding 32-bit
element in the second source register, accumulating the result into the
corresponding 32-bit element of the destination register.
In Armv8.2 and Armv8.3, this is an OPTIONAL instruction.
From Armv8.4 it is mandatory for all implementations to support it.
ID_ISAR6.DP indicates whether this instruction is supported.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
1
1
1
1
1
1
0
0
0
1
0
1
1
0
1
0
0
VSDOT{<q>}.S8 <Dd>, <Dn>, <Dm>
1
VSDOT{<q>}.S8 <Qd>, <Qn>, <Qm>
if !IsFeatureImplemented(FEAT_DotProd) then Undefined(); end;
if Q == '1' && (Vd[0] == '1' || Vn[0] == '1' || Vm[0] == '1') then Undefined(); end;
let signed : boolean = U=='0';
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
let esize : integer{} = 32;
let regs : integer = if Q == '1' then 2 else 1;
1
1
1
1
1
1
0
0
0
1
0
1
1
0
1
0
0
VSDOT{<q>}.S8 <Dd>, <Dn>, <Dm>
1
VSDOT{<q>}.S8 <Qd>, <Qn>, <Qm>
if InITBlock() then UnpredictableProcedure(); end;
if !IsFeatureImplemented(FEAT_DotProd) then Undefined(); end;
if Q == '1' && (Vd[0] == '1' || Vn[0] == '1' || Vm[0] == '1') then Undefined(); end;
let signed : boolean = U=='0';
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
let esize : integer{} = 32;
let regs : integer = if Q == '1' then 2 else 1;
<q>
See Standard assembler syntax fields.
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
<Dn>
Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.
<Dm>
Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.
<Qd>
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.
<Qn>
Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.
<Qm>
Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.
var operand1 : bits(64);
var operand2 : bits(64);
var result : bits(64);
CheckAdvSIMDEnabled();
for r = 0 to regs-1 do
operand1 = D(n+r);
operand2 = D(m+r);
result = D(d+r);
var element1, element2 : integer;
for e = 0 to 1 do
var res : integer = 0;
for i = 0 to 3 do
if signed then
element1 = SInt(operand1[(4 * e + i)*:(esize DIV 4)]);
element2 = SInt(operand2[(4 * e + i)*:(esize DIV 4)]);
else
element1 = UInt(operand1[(4 * e + i)*:(esize DIV 4)]);
element2 = UInt(operand2[(4 * e + i)*:(esize DIV 4)]);
end;
res = res + element1 * element2;
end;
result[e*:esize] = result[e*:esize] + res;
end;
D(d+r) = result;
end;
2026-03-26 20:27:25
2026-03_rel