VSELEQ, VSELGE, VSELGT, VSELVS Floating-point conditional select Floating-point conditional select allows the destination register to take the value in either one or the other source register according to the condition codes in the APSR. It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) . 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 1 VSELEQ.F16 <Sd>, <Sn>, <Sm> 0 0 1 0 VSELEQ.F32 <Sd>, <Sn>, <Sm> 0 0 1 1 VSELEQ.F64 <Dd>, <Dn>, <Dm> 1 0 0 1 VSELGE.F16 <Sd>, <Sn>, <Sm> 1 0 1 0 VSELGE.F32 <Sd>, <Sn>, <Sm> 1 0 1 1 VSELGE.F64 <Dd>, <Dn>, <Dm> 1 1 0 1 VSELGT.F16 <Sd>, <Sn>, <Sm> 1 1 1 0 VSELGT.F32 <Sd>, <Sn>, <Sm> 1 1 1 1 VSELGT.F64 <Dd>, <Dn>, <Dm> 0 1 0 1 VSELVS.F16 <Sd>, <Sn>, <Sm> 0 1 1 0 VSELVS.F32 <Sd>, <Sn>, <Sm> 0 1 1 1 VSELVS.F64 <Dd>, <Dn>, <Dm> if size == '00' || (size == '01' && !IsFeatureImplemented(FEAT_FP16)) then Undefined(); end; let esize : integer{} = 8 << UInt(size); let d : integer = if size == '11' then UInt(D::Vd) else UInt(Vd::D); let n : integer = if size == '11' then UInt(N::Vn) else UInt(Vn::N); let m : integer = if size == '11' then UInt(M::Vm) else UInt(Vm::M); let condition : bits(4) = cc::(cc[1] XOR cc[0])::'0'; 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 1 VSELEQ.F16 <Sd>, <Sn>, <Sm> 0 0 1 0 VSELEQ.F32 <Sd>, <Sn>, <Sm> 0 0 1 1 VSELEQ.F64 <Dd>, <Dn>, <Dm> 1 0 0 1 VSELGE.F16 <Sd>, <Sn>, <Sm> 1 0 1 0 VSELGE.F32 <Sd>, <Sn>, <Sm> 1 0 1 1 VSELGE.F64 <Dd>, <Dn>, <Dm> 1 1 0 1 VSELGT.F16 <Sd>, <Sn>, <Sm> 1 1 1 0 VSELGT.F32 <Sd>, <Sn>, <Sm> 1 1 1 1 VSELGT.F64 <Dd>, <Dn>, <Dm> 0 1 0 1 VSELVS.F16 <Sd>, <Sn>, <Sm> 0 1 1 0 VSELVS.F32 <Sd>, <Sn>, <Sm> 0 1 1 1 VSELVS.F64 <Dd>, <Dn>, <Dm> if InITBlock() then UnpredictableProcedure(); end; if size == '00' || (size == '01' && !IsFeatureImplemented(FEAT_FP16)) then Undefined(); end; let esize : integer{} = 8 << UInt(size); let d : integer = if size == '11' then UInt(D::Vd) else UInt(Vd::D); let n : integer = if size == '11' then UInt(N::Vn) else UInt(Vn::N); let m : integer = if size == '11' then UInt(M::Vm) else UInt(Vm::M); let condition : bits(4) = cc::(cc[1] XOR cc[0])::'0'; InITBlock() The instruction executes as if it passes the Condition code check. The instruction executes as NOP. This means it behaves as if it fails the Condition code check. <Sd> Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field. <Sn> Is the 32-bit name of the first SIMD&FP source register, encoded in the "Vn:N" field. <Sm> Is the 32-bit name of the second SIMD&FP source register, encoded in the "Vm:M" field. <Dd> Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field. <Dn> Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field. <Dm> Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field. EncodingSpecificOperations(); CheckVFPEnabled(TRUE); case esize of when 16 => H(d) = if ConditionHolds(condition) then H(n) else H(m); when 32 => S(d) = if ConditionHolds(condition) then S(n) else S(m); when 64 => D(d) = if ConditionHolds(condition) then D(n) else D(m); end; 2026-03-26 20:27:25 2026-03_rel