VSHRN
Vector Shift Right Narrow
Vector Shift Right Narrow takes each element in a vector,
right shifts them by an immediate value, and places the truncated
results in the destination vector. For rounded results, see
VRSHRN.
The operand elements can be 16-bit, 32-bit, or 64-bit integers.
There is no distinction between signed and unsigned integers. The
destination elements are half the size of the source elements.
Depending on settings in the CPACR,
NSACR, and
HCPTR registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information see Enabling Advanced
SIMD and floating-point support.
Related encodings: See Advanced SIMD one register and modified immediate for the T32 instruction set, or Advanced SIMD one register and modified immediate for the A32 instruction set.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
1
1
1
1
0
0
1
0
1
!= 000xxx
1
0
0
0
0
0
1
VSHRN{<c>}{<q>}.I<size> <Dd>, <Qm>, #<imm>
if imm6 == '000xxx' then See("Related encodings"); end;
if Vm[0] == '1' then Undefined(); end;
let esize : integer{} = 8 << HighestSetBitNZ(imm6[5:3]);
let elements : integer = 64 DIV esize;
let shift_amount : integer = (2 * esize) - UInt(imm6);
let d : integer = UInt(D::Vd);
let m : integer = UInt(M::Vm);
1
1
1
0
1
1
1
1
1
!= 000xxx
1
0
0
0
0
0
1
VSHRN{<c>}{<q>}.I<size> <Dd>, <Qm>, #<imm>
if imm6 == '000xxx' then See("Related encodings"); end;
if Vm[0] == '1' then Undefined(); end;
let esize : integer{} = 8 << HighestSetBitNZ(imm6[5:3]);
let elements : integer = 64 DIV esize;
let shift_amount : integer = (2 * esize) - UInt(imm6);
let d : integer = UInt(D::Vd);
let m : integer = UInt(M::Vm);
<c>
For the "A1" variant: see Standard assembler syntax fields. This encoding must be unconditional.
<c>
For the "T1" variant: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<size>
Is the data size for the elements of the vectors,
imm6
<size>
001xxx
16
01xxxx
32
1xxxxx
64
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
<Qm>
Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.
<imm>
Is an immediate value, in the range 1 to <size>/2, encoded in the "imm6" field as <size>/2 - <imm>.
if ConditionPassed() then
EncodingSpecificOperations();
CheckAdvSIMDEnabled();
for e = 0 to elements-1 do
let result : bits(2*esize) = LSR(Qin(m>>1)[e*:(2*esize)], shift_amount);
D(d)[e*:esize] = result[esize-1:0];
end;
end;
2026-03-26 20:27:25
2026-03_rel