VSLI
Vector Shift Left and Insert
Vector Shift Left and Insert takes each element in the operand
vector, left shifts them by an immediate value, and inserts the
results in the destination vector. Bits shifted out of the left
of each element are lost.
The elements must all be the same size, and can be 8-bit,
16-bit, 32-bit, or 64-bit. There is no distinction between data
types.
Depending on settings in the CPACR,
NSACR, and
HCPTR registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information see Enabling Advanced
SIMD and floating-point support.
Related encodings: See Advanced SIMD one register and modified immediate for the T32 instruction set, or Advanced SIMD one register and modified immediate for the A32 instruction set.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
1
1
1
1
0
0
1
1
1
0
1
0
1
1
0
VSLI{<c>}{<q>}.<size> {<Dd>, }<Dm>, #<imm>
1
VSLI{<c>}{<q>}.<size> {<Qd>, }<Qm>, #<imm>
if (L::imm6) == '0000xxx' then See("Related encodings"); end;
if Q == '1' && (Vd[0] == '1' || Vm[0] == '1') then Undefined(); end;
let esize : integer{} = 8 << HighestSetBitNZ((L::imm6)[6:3]);
let elements : integer = 64 DIV esize;
let shift_amount : integer = UInt(L::imm6) - esize;
let d : integer = UInt(D::Vd);
let m : integer = UInt(M::Vm);
let regs : integer = if Q == '0' then 1 else 2;
1
1
1
1
1
1
1
1
1
0
1
0
1
1
0
VSLI{<c>}{<q>}.<size> {<Dd>, }<Dm>, #<imm>
1
VSLI{<c>}{<q>}.<size> {<Qd>, }<Qm>, #<imm>
if (L::imm6) == '0000xxx' then See("Related encodings"); end;
if Q == '1' && (Vd[0] == '1' || Vm[0] == '1') then Undefined(); end;
let esize : integer{} = 8 << HighestSetBitNZ((L::imm6)[6:3]);
let elements : integer = 64 DIV esize;
let shift_amount : integer = UInt(L::imm6) - esize;
let d : integer = UInt(D::Vd);
let m : integer = UInt(M::Vm);
let regs : integer = if Q == '0' then 1 else 2;
<c>
For the "A1 128-bit SIMD vector" and "A1 64-bit SIMD vector" variants: see Standard assembler syntax fields. This encoding must be unconditional.
<c>
For the "T1 128-bit SIMD vector" and "T1 64-bit SIMD vector" variants: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<size>
Is the data size for the elements of the vectors,
L
imm6
<size>
0
001xxx
8
0
01xxxx
16
0
1xxxxx
32
1
xxxxxx
64
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
<Dm>
Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.
<imm>
Is an immediate value, in the range 0 to <size>-1, encoded in the "imm6" field.
<Qd>
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.
<Qm>
Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.
if ConditionPassed() then
EncodingSpecificOperations();
CheckAdvSIMDEnabled();
let mask : bits(esize) = LSL{}(Ones{esize}, shift_amount);
for r = 0 to regs-1 do
for e = 0 to elements-1 do
let shifted_op : bits(esize) = LSL{}(D(m+r)[e*:esize], shift_amount);
D(d+r)[e*:esize] = (D(d+r)[e*:esize] AND NOT(mask)) OR shifted_op;
end;
end;
end;
2026-03-26 20:27:25
2026-03_rel