VST1 (multiple single elements)
Store multiple single elements from one, two, three, or four registers
Store multiple single elements from one, two, three, or four
registers stores elements to memory from one, two, three, or four
registers, without interleaving. Every element of each register is
stored. For details of the addressing mode, see
Advanced SIMD addressing mode.
Depending on settings in the CPACR,
NSACR, and
HCPTR registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information, see Enabling Advanced
SIMD and floating-point support.
For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly VST1 (multiple single elements).
Related encodings: See Advanced SIMD element or structure load/store for the T32 instruction set, or Advanced SIMD element or structure load/store for the A32 instruction set.
For more information about <Rn>, !, and <Rm>, see Advanced SIMD addressing mode.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
,
A2
,
A3
and
A4
)
and
T32 (
T1
,
T2
,
T3
and
T4
)
.
1
1
1
1
0
1
0
0
0
0
0
0
1
1
1
1
1
1
1
VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]
1
1
0
1
VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]!
N
N
Z
N
VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm>
if align[1] == '1' then Undefined(); end;
let alignment : integer{} = if align == '00' then 1 else 4 << UInt(align);
let regs : integer = 1;
let ebytes : integer{} = 1 << UInt(size);
let elements : integer = 8 DIV ebytes;
let d : integer = UInt(D::Vd);
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let wback : boolean = (m != 15);
let register_index : boolean = (m != 15 && m != 13);
if n == 15 then UnpredictableProcedure(); end;
1
1
1
1
0
1
0
0
0
0
0
1
0
1
0
1
1
1
1
VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]
1
1
0
1
VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]!
N
N
Z
N
VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm>
if align == '11' then Undefined(); end;
let alignment : integer{} = if align == '00' then 1 else 4 << UInt(align);
let regs : integer = 2;
let ebytes : integer{} = 1 << UInt(size);
let elements : integer = 8 DIV ebytes;
let d : integer = UInt(D::Vd);
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let wback : boolean = (m != 15);
let register_index : boolean = (m != 15 && m != 13);
if n == 15 || d+regs > 32 then UnpredictableProcedure(); end;
d+regs > 32
The memory locations specified by the instruction and the number of registers specified by the instruction become UNKNOWN. If the instruction specifies writeback, then that register becomes UNKNOWN. This behavior does not affect any other memory locations.
1
1
1
1
0
1
0
0
0
0
0
0
1
1
0
1
1
1
1
VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]
1
1
0
1
VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]!
N
N
Z
N
VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm>
if align[1] == '1' then Undefined(); end;
let alignment : integer{} = if align == '00' then 1 else 4 << UInt(align);
let regs : integer = 3;
let ebytes : integer{} = 1 << UInt(size);
let elements : integer = 8 DIV ebytes;
let d : integer = UInt(D::Vd);
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let wback : boolean = (m != 15);
let register_index : boolean = (m != 15 && m != 13);
if n == 15 || d+regs > 32 then UnpredictableProcedure(); end;
d+regs > 32
The memory locations specified by the instruction and the number of registers specified by the instruction become UNKNOWN. If the instruction specifies writeback, then that register becomes UNKNOWN. This behavior does not affect any other memory locations.
1
1
1
1
0
1
0
0
0
0
0
0
0
1
0
1
1
1
1
VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]
1
1
0
1
VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]!
N
N
Z
N
VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm>
let regs : integer = 4;
let alignment : integer{} = if align == '00' then 1 else 4 << UInt(align);
let ebytes : integer{} = 1 << UInt(size);
let elements : integer = 8 DIV ebytes;
let d : integer = UInt(D::Vd);
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let wback : boolean = (m != 15);
let register_index : boolean = (m != 15 && m != 13);
if n == 15 || d+regs > 32 then UnpredictableProcedure(); end;
d+regs > 32
The memory locations specified by the instruction and the number of registers specified by the instruction become UNKNOWN. If the instruction specifies writeback, then that register becomes UNKNOWN. This behavior does not affect any other memory locations.
1
1
1
1
1
0
0
1
0
0
0
0
1
1
1
1
1
1
1
VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]
1
1
0
1
VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]!
N
N
Z
N
VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm>
if align[1] == '1' then Undefined(); end;
let alignment : integer{} = if align == '00' then 1 else 4 << UInt(align);
let regs : integer = 1;
let ebytes : integer{} = 1 << UInt(size);
let elements : integer = 8 DIV ebytes;
let d : integer = UInt(D::Vd);
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let wback : boolean = (m != 15);
let register_index : boolean = (m != 15 && m != 13);
if n == 15 then UnpredictableProcedure(); end;
1
1
1
1
1
0
0
1
0
0
0
1
0
1
0
1
1
1
1
VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]
1
1
0
1
VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]!
N
N
Z
N
VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm>
if align == '11' then Undefined(); end;
let alignment : integer{} = if align == '00' then 1 else 4 << UInt(align);
let regs : integer = 2;
let ebytes : integer{} = 1 << UInt(size);
let elements : integer = 8 DIV ebytes;
let d : integer = UInt(D::Vd);
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let wback : boolean = (m != 15);
let register_index : boolean = (m != 15 && m != 13);
if n == 15 || d+regs > 32 then UnpredictableProcedure(); end;
d+regs > 32
The memory locations specified by the instruction and the number of registers specified by the instruction become UNKNOWN. If the instruction specifies writeback, then that register becomes UNKNOWN. This behavior does not affect any other memory locations.
1
1
1
1
1
0
0
1
0
0
0
0
1
1
0
1
1
1
1
VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]
1
1
0
1
VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]!
N
N
Z
N
VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm>
if align[1] == '1' then Undefined(); end;
let alignment : integer{} = if align == '00' then 1 else 4 << UInt(align);
let regs : integer = 3;
let ebytes : integer{} = 1 << UInt(size);
let elements : integer = 8 DIV ebytes;
let d : integer = UInt(D::Vd);
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let wback : boolean = (m != 15);
let register_index : boolean = (m != 15 && m != 13);
if n == 15 || d+regs > 32 then UnpredictableProcedure(); end;
d+regs > 32
The memory locations specified by the instruction and the number of registers specified by the instruction become UNKNOWN. If the instruction specifies writeback, then that register becomes UNKNOWN. This behavior does not affect any other memory locations.
1
1
1
1
1
0
0
1
0
0
0
0
0
1
0
1
1
1
1
VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]
1
1
0
1
VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]!
N
N
Z
N
VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm>
let regs : integer = 4;
let alignment : integer{} = if align == '00' then 1 else 4 << UInt(align);
let ebytes : integer{} = 1 << UInt(size);
let elements : integer = 8 DIV ebytes;
let d : integer = UInt(D::Vd);
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let wback : boolean = (m != 15);
let register_index : boolean = (m != 15 && m != 13);
if n == 15 || d+regs > 32 then UnpredictableProcedure(); end;
d+regs > 32
The memory locations specified by the instruction and the number of registers specified by the instruction become UNKNOWN. If the instruction specifies writeback, then that register becomes UNKNOWN. This behavior does not affect any other memory locations.
<c>
For the "A1 Offset", "A1 Post-indexed", "A2 Offset", "A2 Post-indexed", "A3 Offset", "A3 Post-indexed", "A4 Offset", and "A4 Post-indexed" variants: see Standard assembler syntax fields. This encoding must be unconditional.
<c>
For the "T1 Offset", "T1 Post-indexed", "T2 Offset", "T2 Post-indexed", "T3 Offset", "T3 Post-indexed", "T4 Offset", and "T4 Post-indexed" variants: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<size>
Is the data size,
size
<size>
00
8
01
16
10
32
11
64
<list>
Is a list containing the 64-bit names of the SIMD&FP registers.
The list must be one of:
{ <Dd> }
Single register. Selects the A1 and T1 encodings of the instruction.
{ <Dd>, <Dd+1> }
Two single-spaced registers. Selects the A2 and T2 encodings of the instruction.
{ <Dd>, <Dd+1>, <Dd+2> }
Three single-spaced registers. Selects the A3 and T3 encodings of the instruction.
{ <Dd>, <Dd+1>, <Dd+2>, <Dd+3> }
Four single-spaced registers. Selects the A4 and T4 encodings of the instruction.
The register <Dd> is encoded in the "D:Vd" field.
<Rn>
Is the general-purpose base register, encoded in the "Rn" field.
<align>
Is the optional alignment.
Whenever <align> is omitted, the standard alignment is used, see Unaligned data access, and is encoded in the "align" field as 0b00.
Whenever <align> is present, the permitted values are:
64
64-bit alignment, encoded in the "align" field as 0b01.
128
128-bit alignment, encoded in the "align" field as 0b10. Available only if <list> contains two or four registers.
256
256-bit alignment, encoded in the "align" field as 0b11. Available only if <list> contains four registers.
: is the preferred separator before the <align> value, but the alignment can be specified as @<align>, see Advanced SIMD addressing mode.
<Rm>
Is the general-purpose index register containing an offset applied after the access, encoded in the "Rm" field.
if ConditionPassed() then
EncodingSpecificOperations();
CheckAdvSIMDEnabled();
var address : bits(32) = R(n);
let nontemporal : boolean = FALSE;
let privileged : boolean = PSTATE.EL != EL0;
let tagchecked : boolean = FALSE;
let accdesc : AccessDescriptor = CreateAccDescASIMD(MemOp_STORE, nontemporal,
tagchecked, privileged);
if !IsAlignedSize(address, alignment) then
let fault : FaultRecord = AlignmentFault(accdesc, ZeroExtend{64}(address));
AArch32_Abort(fault);
end;
for r = 0 to regs-1 do
for e = 0 to elements-1 do
if ebytes != 8 then
MemU{8*ebytes}(address) = D(d+r)[e*:(8*ebytes)];
else
if !IsAlignedSize(address, ebytes) && AlignmentEnforced() then
let fault : FaultRecord = AlignmentFault(accdesc, ZeroExtend{64}(address));
AArch32_Abort(fault);
end;
let data : bits(64) = D(d+r)[e*:64];
if BigEndian(AccessType_ASIMD) then
MemU{32}(address) = data[63:32];
MemU{32}(address+4) = data[31:0];
else
MemU{32}(address) = data[31:0];
MemU{32}(address+4) = data[63:32];
end;
end;
address = address + ebytes;
end;
end;
if wback then
if register_index then
R(n) = R(n) + R(m);
else
R(n) = R(n) + 8*regs;
end;
end;
end;
2026-03-26 20:27:25
2026-03_rel