VST4 (single 4-element structure from one lane)
Store single 4-element structure from one lane of four registers
Store single 4-element structure from one lane of four registers
stores one 4-element structure to memory from corresponding elements
of four registers. For details of the addressing mode, see
Advanced SIMD addressing mode.
Depending on settings in the CPACR,
NSACR, and
HCPTR registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information, see Enabling Advanced
SIMD and floating-point support.
For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly VST4 (single 4-element structure from one lane).
For more information about the variants of this instruction, see Advanced SIMD addressing mode.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
,
A2
and
A3
)
and
T32 (
T1
,
T2
and
T3
)
.
1
1
1
1
0
1
0
0
1
0
0
0
0
1
1
1
1
1
1
VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]
1
1
0
1
VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]!
N
N
Z
N
VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm>
if size == '11' then Undefined(); end;
if size != '00' then See("Related encodings"); end;
let ebytes : integer{} = 1;
let index : integer = UInt(index_align[3:1]);
let inc : integer = 1;
let alignment : integer{} = if index_align[0] == '0' then 1 else 4;
let d : integer = UInt(D::Vd);
let d2 : integer = d + inc;
let d3 : integer = d2 + inc;
let d4 : integer = d3 + inc;
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let wback : boolean = (m != 15);
let register_index : boolean = (m != 15 && m != 13);
if n == 15 || d4 > 31 then UnpredictableProcedure(); end;
d4 > 31
The memory locations specified by the instruction and the number of registers specified by the instruction become UNKNOWN. If the instruction specifies writeback, then that register becomes UNKNOWN. This behavior does not affect any other memory locations.
1
1
1
1
0
1
0
0
1
0
0
0
1
1
1
1
1
1
1
VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]
1
1
0
1
VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]!
N
N
Z
N
VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm>
if size == '11' then Undefined(); end;
if size != '01' then See("Related encodings"); end;
let ebytes : integer{} = 2;
let index : integer = UInt(index_align[3:2]);
let inc : integer = if index_align[1] == '0' then 1 else 2;
let alignment : integer{} = if index_align[0] == '0' then 1 else 8;
let d : integer = UInt(D::Vd);
let d2 : integer = d + inc;
let d3 : integer = d2 + inc;
let d4 : integer = d3 + inc;
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let wback : boolean = (m != 15);
let register_index : boolean = (m != 15 && m != 13);
if n == 15 || d4 > 31 then UnpredictableProcedure(); end;
d4 > 31
The memory locations specified by the instruction and the number of registers specified by the instruction become UNKNOWN. If the instruction specifies writeback, then that register becomes UNKNOWN. This behavior does not affect any other memory locations.
1
1
1
1
0
1
0
0
1
0
0
1
0
1
1
1
1
1
1
VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]
1
1
0
1
VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]!
N
N
Z
N
VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm>
if size == '11' then Undefined(); end;
if size != '10' then See("Related encodings"); end;
if index_align[1:0] == '11' then Undefined(); end;
let ebytes : integer{} = 4;
let index : integer = UInt(index_align[3]);
let inc : integer = if index_align[2] == '0' then 1 else 2;
let alignment : integer{} = if index_align[1:0] == '00' then 1 else 4 << UInt(index_align[1:0]);
let d : integer = UInt(D::Vd);
let d2 : integer = d + inc;
let d3 : integer = d2 + inc;
let d4 : integer = d3 + inc;
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let wback : boolean = (m != 15);
let register_index : boolean = (m != 15 && m != 13);
if n == 15 || d4 > 31 then UnpredictableProcedure(); end;
d4 > 31
The memory locations specified by the instruction and the number of registers specified by the instruction become UNKNOWN. If the instruction specifies writeback, then that register becomes UNKNOWN. This behavior does not affect any other memory locations.
1
1
1
1
1
0
0
1
1
0
0
0
0
1
1
1
1
1
1
VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]
1
1
0
1
VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]!
N
N
Z
N
VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm>
if size == '11' then Undefined(); end;
if size != '00' then See("Related encodings"); end;
let ebytes : integer{} = 1;
let index : integer = UInt(index_align[3:1]);
let inc : integer = 1;
let alignment : integer{} = if index_align[0] == '0' then 1 else 4;
let d : integer = UInt(D::Vd);
let d2 : integer = d + inc;
let d3 : integer = d2 + inc;
let d4 : integer = d3 + inc;
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let wback : boolean = (m != 15);
let register_index : boolean = (m != 15 && m != 13);
if n == 15 || d4 > 31 then UnpredictableProcedure(); end;
d4 > 31
The memory locations specified by the instruction and the number of registers specified by the instruction become UNKNOWN. If the instruction specifies writeback, then that register becomes UNKNOWN. This behavior does not affect any other memory locations.
1
1
1
1
1
0
0
1
1
0
0
0
1
1
1
1
1
1
1
VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]
1
1
0
1
VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]!
N
N
Z
N
VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm>
if size == '11' then Undefined(); end;
if size != '01' then See("Related encodings"); end;
let ebytes : integer{} = 2;
let index : integer = UInt(index_align[3:2]);
let inc : integer = if index_align[1] == '0' then 1 else 2;
let alignment : integer{} = if index_align[0] == '0' then 1 else 8;
let d : integer = UInt(D::Vd);
let d2 : integer = d + inc;
let d3 : integer = d2 + inc;
let d4 : integer = d3 + inc;
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let wback : boolean = (m != 15);
let register_index : boolean = (m != 15 && m != 13);
if n == 15 || d4 > 31 then UnpredictableProcedure(); end;
d4 > 31
The memory locations specified by the instruction and the number of registers specified by the instruction become UNKNOWN. If the instruction specifies writeback, then that register becomes UNKNOWN. This behavior does not affect any other memory locations.
1
1
1
1
1
0
0
1
1
0
0
1
0
1
1
1
1
1
1
VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]
1
1
0
1
VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]!
N
N
Z
N
VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm>
if size == '11' then Undefined(); end;
if size != '10' then See("Related encodings"); end;
if index_align[1:0] == '11' then Undefined(); end;
let ebytes : integer{} = 4;
let index : integer = UInt(index_align[3]);
let inc : integer = if index_align[2] == '0' then 1 else 2;
let alignment : integer{} = if index_align[1:0] == '00' then 1 else 4 << UInt(index_align[1:0]);
let d : integer = UInt(D::Vd);
let d2 : integer = d + inc;
let d3 : integer = d2 + inc;
let d4 : integer = d3 + inc;
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let wback : boolean = (m != 15);
let register_index : boolean = (m != 15 && m != 13);
if n == 15 || d4 > 31 then UnpredictableProcedure(); end;
d4 > 31
The memory locations specified by the instruction and the number of registers specified by the instruction become UNKNOWN. If the instruction specifies writeback, then that register becomes UNKNOWN. This behavior does not affect any other memory locations.
<c>
For the "A1 Offset", "A1 Post-indexed", "A2 Offset", "A2 Post-indexed", "A3 Offset", and "A3 Post-indexed" variants: see Standard assembler syntax fields. This encoding must be unconditional.
<c>
For the "T1 Offset", "T1 Post-indexed", "T2 Offset", "T2 Post-indexed", "T3 Offset", and "T3 Post-indexed" variants: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<size>
Is the data size,
size
<size>
00
8
01
16
10
32
<list>
Is a list containing the 64-bit names of the four SIMD&FP registers holding the element.
The list must be one of:
{ <Dd>[<index>], <Dd+1>[<index>], <Dd+2>[<index>], <Dd+3>[<index>] }
Single-spaced registers, encoded as "spacing" = 0.
{ <Dd>[<index>], <Dd+2>[<index>], <Dd+4>[<index>], <Dd+6>[<index>] }
Double-spaced registers, encoded as "spacing" = 1. Not permitted when <size> == 8.
The encoding of "spacing" depends on <size>:
<size> == 16
"spacing" is encoded in the "index_align<1>" field.
<size> == 32
"spacing" is encoded in the "index_align<2>" field.
The register <Dd> is encoded in the "D:Vd" field.
The permitted values and encoding of <index> depend on <size>:
<size> == 8
<index> is in the range 0 to 7, encoded in the "index_align<3:1>" field.
<size> == 16
<index> is in the range 0 to 3, encoded in the "index_align<3:2>" field.
<size> == 32
<index> is 0 or 1, encoded in the "index_align<3>" field.
<Rn>
Is the general-purpose base register, encoded in the "Rn" field.
<align>
Is the optional alignment.
Whenever <align> is omitted, the standard alignment is used, see Unaligned data access, and the encoding depends on <size>:
<size> == 8
Encoded in the "index_align<0>" field as 0.
<size> == 16
Encoded in the "index_align<0>" field as 0.
<size> == 32
Encoded in the "index_align<1:0>" field as 0b00.
Whenever <align> is present, the permitted values and encoding depend on <size>:
<size> == 8
<align> is 32, meaning 32-bit alignment, encoded in the "index_align<0>" field as 1.
<size> == 16
<align> is 64, meaning 64-bit alignment, encoded in the "index_align<0>" field as 1.
<size> == 32
<align> can be 64 or 128. 64-bit alignment is encoded in the "index_align<1:0>" field as 0b01, and 128-bit alignment is encoded in the "index_align<1:0>" field as 0b10.
: is the preferred separator before the <align> value, but the alignment can be specified as @<align>, see Advanced SIMD addressing mode.
<Rm>
Is the general-purpose index register containing an offset applied after the access, encoded in the "Rm" field.
if ConditionPassed() then
EncodingSpecificOperations();
CheckAdvSIMDEnabled();
let address : bits(32) = R(n);
let nontemporal : boolean = FALSE;
let privileged : boolean = PSTATE.EL != EL0;
let tagchecked : boolean = FALSE;
let accdesc : AccessDescriptor = CreateAccDescASIMD(MemOp_STORE, nontemporal,
tagchecked, privileged);
if !IsAlignedSize(address, alignment) then
let fault : FaultRecord = AlignmentFault(accdesc, ZeroExtend{64}(address));
AArch32_Abort(fault);
end;
MemU{8*ebytes}(address ) = D(d)[index*:(8*ebytes)];
MemU{8*ebytes}(address+ebytes ) = D(d2)[index*:(8*ebytes)];
MemU{8*ebytes}(address+2*ebytes) = D(d3)[index*:(8*ebytes)];
MemU{8*ebytes}(address+3*ebytes) = D(d4)[index*:(8*ebytes)];
if wback then
if register_index then
R(n) = R(n) + R(m);
else
R(n) = R(n) + 4*ebytes;
end;
end;
end;
2026-03-26 20:27:25
2026-03_rel