VUSDOT (vector)
Dot Product vector form with mixed-sign integers
Dot Product vector form with mixed-sign integers. This instruction performs the dot product of
the four unsigned 8-bit integer values in each 32-bit element of the first source register with
the four signed 8-bit integer values in the corresponding 32-bit element of the second source
register, accumulating the result into the corresponding 32-bit element of the destination
register.
From Armv8.2, this is an OPTIONAL instruction. ID_ISAR6.I8MM
indicates whether this instruction is supported in the T32 and A32 instruction sets.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
1
1
1
1
1
1
0
0
1
1
0
1
1
0
1
0
0
VUSDOT{<q>}.S8 <Dd>, <Dn>, <Dm>
1
VUSDOT{<q>}.S8 <Qd>, <Qn>, <Qm>
if !IsFeatureImplemented(FEAT_AA32I8MM) then Undefined(); end;
if Q == '1' && (Vd[0] == '1' || Vn[0] == '1' || Vm[0] == '1') then Undefined(); end;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
let regs : integer = if Q == '1' then 2 else 1;
1
1
1
1
1
1
0
0
1
1
0
1
1
0
1
0
0
VUSDOT{<q>}.S8 <Dd>, <Dn>, <Dm>
1
VUSDOT{<q>}.S8 <Qd>, <Qn>, <Qm>
if InITBlock() then UnpredictableProcedure(); end;
if !IsFeatureImplemented(FEAT_AA32I8MM) then Undefined(); end;
if Q == '1' && (Vd[0] == '1' || Vn[0] == '1' || Vm[0] == '1') then Undefined(); end;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
let regs : integer = if Q == '1' then 2 else 1;
<q>
See Standard assembler syntax fields.
<Dd>
Is the 64-bit name of the SIMD&FP third source and destination register, encoded in the "D:Vd" field.
<Dn>
Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.
<Dm>
Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.
<Qd>
Is the 128-bit name of the SIMD&FP third source and destination register, encoded in the "D:Vd" field as <Qd>*2.
<Qn>
Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.
<Qm>
Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.
CheckAdvSIMDEnabled();
var operand1 : bits(64);
var operand2 : bits(64);
var result : bits(64);
for r = 0 to regs-1 do
operand1 = Din(n+r);
operand2 = Din(m+r);
result = Din(d+r);
for e = 0 to 1 do
var res : bits(32) = result[e*:32];
for b = 0 to 3 do
let element1 : integer = UInt(operand1[(4 * e + b)*:8]);
let element2 : integer = SInt(operand2[(4 * e + b)*:8]);
res = res + element1 * element2;
end;
result[e*:32] = res;
end;
D(d+r) = result;
end;
2026-03-26 20:27:25
2026-03_rel