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BFC -- AArch32

BFC

Bit Field Clear clears any number of adjacent bits at any position in a register, without affecting the other bits in the register.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
!= 11110111110msbRdlsb0011111
condRn

Encoding

BFC{<c>}{<q>} <Rd>, #<lsb>, #<width>

Decode for this encoding

let d : integer = UInt(Rd); let msbit : integer{} = UInt(msb); let lsbit : integer{} = UInt(lsb); if d == 15 then UnpredictableProcedure(); end; if msbit < lsbit then UnpredictableProcedure(); end;

CONSTRAINED UNPREDICTABLE behavior

If msbit < lsbit, then one of the following behaviors must occur:

T1

15141312111098765432101514131211109876543210
11110(0)11011011110imm3Rdimm2(0)msb
op1Rn

Encoding

BFC{<c>}{<q>} <Rd>, #<lsb>, #<width>

Decode for this encoding

let d : integer = UInt(Rd); let msbit : integer{} = UInt(msb); let lsbit : integer{} = UInt(imm3::imm2); // Armv8-A removes UNPREDICTABLE for R13 if d == 15 then UnpredictableProcedure(); end; if msbit < lsbit then UnpredictableProcedure(); end;

CONSTRAINED UNPREDICTABLE behavior

If msbit < lsbit, then one of the following behaviors must occur:

For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>

See Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<Rd>

Is the general-purpose destination register, encoded in the "Rd" field.

<lsb>

For the "A1" variant: is the least significant bit to be cleared, in the range 0 to 31, encoded in the "lsb" field.

For the "T1" variant: is the least significant bit that is to be cleared, in the range 0 to 31, encoded in the "imm3:imm2" field.

<width>

Is the number of bits to be cleared, in the range 1 to 32-<lsb>, encoded in the "msb" field as <lsb>+<width>-1.

Operation

if ConditionPassed() then EncodingSpecificOperations(); R(d)[msbit:lsbit] = Replicate{(msbit-lsbit)+1}('0'); // Other bits of R[d] are unchanged end;

Operational information

This instruction is a data-independent-time instruction as described in About the DIT bit.


2026-03_rel 2026-03-26 20:48:11

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