BX -- AArch32

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BX -- AArch32

BX

Branch and Exchange causes a branch to an address and instruction set specified by a register.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
!= 1111				0	0	0	1	0	0	1	0	(1)	(1)	(1)	(1)	(1)	(1)	(1)	(1)	(1)	(1)	(1)	(1)	0	0	0	1	Rm
cond									op0

Encoding

BX{<c>}{<q>} <Rm>

Decode for this encoding

let m : integer = UInt(Rm);

T1

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	0	0	0	1	1	1	0	Rm				(0)	(0)	(0)
								L

Encoding

BX{<c>}{<q>} <Rm>

Decode for this encoding

let m : integer = UInt(Rm); if InITBlock() && !LastInITBlock() then UnpredictableProcedure(); end;

For more information about the CONSTRAINED UNPREDICTABLE behavior, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>	See Standard assembler syntax fields.

<q>	See Standard assembler syntax fields.

<Rm>	For the "A1" variant: is the general-purpose register holding the address to be branched to, encoded in the "Rm" field. The PC can be used.
	For the "T1" variant: is the general-purpose register holding the address to be branched to, encoded in the "Rm" field. The PC can be used. Note If <Rm> is the PC at a non word-aligned address, it results in UNPREDICTABLE behavior because the address passed to the BXWritePC() pseudocode function has bits<1:0> = '10'.

Operation

if ConditionPassed() then EncodingSpecificOperations(); BXWritePC(R(m), BranchType_INDIR); end;

2026-03_rel 2026-03-26 20:48:11

BX

A1

Encoding

Decode for this encoding

T1

Encoding

Decode for this encoding

Assembler Symbols

Note

Operation