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BXJ -- AArch32

BXJ

Branch and Exchange, previously Branch and Exchange Jazelle.

BXJ behaves as a BX instruction, see BX. This means it causes a branch to an address and instruction set specified by a register.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
!= 111100010010(1)(1)(1)(1)(1)(1)(1)(1)(1)(1)(1)(1)0010Rm
condop0

Encoding

BXJ{<c>}{<q>} <Rm>

Decode for this encoding

let m : integer = UInt(Rm); if m == 15 then UnpredictableProcedure(); end;

T1

15141312111098765432101514131211109876543210
111100111100Rm10(0)0(1)(1)(1)(1)(0)(0)(0)(0)(0)(0)(0)(0)

Encoding

BXJ{<c>}{<q>} <Rm>

Decode for this encoding

let m : integer = UInt(Rm); // Armv8-A removes UNPREDICTABLE for R13 if m == 15 then UnpredictableProcedure(); end; if InITBlock() && !LastInITBlock() then UnpredictableProcedure(); end;

For more information about the CONSTRAINED UNPREDICTABLE behavior, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>

See Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<Rm>

Is the general-purpose register holding the address to be branched to, encoded in the "Rm" field.

Operation

if ConditionPassed() then EncodingSpecificOperations(); BXWritePC(R(m), BranchType_INDIR); end;


2026-03_rel 2026-03-26 20:48:11

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