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CRC32 -- AArch32

CRC32

CRC32 performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, or 32 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x04C11DB7 is used for the CRC calculation.

In an Armv8.0 implementation, this is an OPTIONAL instruction. From Armv8.1, it is mandatory for all implementations to implement this instruction.


Note

ID_ISAR5.CRC32 indicates whether this instruction is supported in the T32 and A32 instruction sets.


It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1
(FEAT_CRC32)

313029282726252423222120191817161514131211109876543210
!= 111100010sz0RnRd(0)(0)0(0)0100Rm
condC

Encoding for the CRC32B variant

Applies when (sz == 00)

CRC32B{<q>} <Rd>, <Rn>, <Rm>

Encoding for the CRC32H variant

Applies when (sz == 01)

CRC32H{<q>} <Rd>, <Rn>, <Rm>

Encoding for the CRC32W variant

Applies when (sz == 10)

CRC32W{<q>} <Rd>, <Rn>, <Rm>

Decode for all variants of this encoding

if !IsFeatureImplemented(FEAT_CRC32) then Undefined(); end; let d : integer = UInt(Rd); let n : integer = UInt(Rn); let m : integer = UInt(Rm); let size : integer{} = 8 << UInt(sz); let crc32c : boolean = (C == '1'); if d == 15 || n == 15 || m == 15 then UnpredictableProcedure(); end; if size == 64 then UnpredictableProcedure(); end; if cond != '1110' then UnpredictableProcedure(); end;

CONSTRAINED UNPREDICTABLE behavior

If size == 64, then one of the following behaviors must occur:

If cond != '1110', then one of the following behaviors must occur:

T1
(FEAT_CRC32)

15141312111098765432101514131211109876543210
111110101100Rn1111Rd10szRm
C

Encoding for the CRC32B variant

Applies when (sz == 00)

CRC32B{<q>} <Rd>, <Rn>, <Rm>

Encoding for the CRC32H variant

Applies when (sz == 01)

CRC32H{<q>} <Rd>, <Rn>, <Rm>

Encoding for the CRC32W variant

Applies when (sz == 10)

CRC32W{<q>} <Rd>, <Rn>, <Rm>

Decode for all variants of this encoding

if InITBlock() then UnpredictableProcedure(); end; if !IsFeatureImplemented(FEAT_CRC32) then Undefined(); end; let d : integer = UInt(Rd); let n : integer = UInt(Rn); let m : integer = UInt(Rm); let size : integer{} = 8 << UInt(sz); let crc32c : boolean = (C == '1'); if d == 15 || n == 15 || m == 15 then UnpredictableProcedure(); end; if size == 64 then UnpredictableProcedure(); end;

CONSTRAINED UNPREDICTABLE behavior

If size == 64, then one of the following behaviors must occur:

For more information about the CONSTRAINED UNPREDICTABLE behavior, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<q>

See Standard assembler syntax fields. A CRC32 instruction must be unconditional.

<Rd>

Is the general-purpose accumulator output register, encoded in the "Rd" field.

<Rn>

Is the general-purpose accumulator input register, encoded in the "Rn" field.

<Rm>

Is the general-purpose data source register, encoded in the "Rm" field.

Operation

if ConditionPassed() then EncodingSpecificOperations(); let acc : bits(32) = R(n); // accumulator let val : bits(size) = R(m)[size-1:0]; // input value let poly : bits(32) = (if crc32c then 0x1EDC6F41 else 0x04C11DB7)[31:0]; let tempacc : bits(32+size) = BitReverse{32}(acc)::Zeros{size}; let tempval : bits(32+size) = BitReverse{size}(val)::Zeros{32}; // Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation R(d) = BitReverse{32}(Poly32Mod2{32+size}(tempacc XOR tempval, poly)); end;

Operational information

This instruction is a data-independent-time instruction as described in About the DIT bit.


2026-03_rel 2026-03-26 20:48:11

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