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ERET -- AArch32
Base Instructions
SIMD&FP Instructions
A32 Instructions by Encoding
T32 Instructions by Encoding
Shared Pseudocode
Proprietary Notice

ERET

Exception Return.

The PE branches to the address held in the register holding the preferred return address, and restores PSTATE from SPSR_<current_mode>.

The register holding the preferred return address is:

The PE checks SPSR_<current_mode> for an illegal return event. See Illegal return events from AArch32 state.

Exception Return is CONSTRAINED UNPREDICTABLE in User mode and System mode.

In Debug state, the T1 encoding of ERET executes the DRPS operation.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
!= 111100010110(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)0110(1)(1)(1)(0)
condop0

Encoding

ERET{<c>}{<q>}

Decode for this encoding

// No additional decoding required

T1

15141312111098765432101514131211109876543210
111100111101111010(0)0(1)(1)(1)(1)00000000
Rnimm8

Encoding

ERET{<c>}{<q>}

Decode for this encoding

if InITBlock() && !LastInITBlock() then UnpredictableProcedure(); end;

For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>

See Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

Operation

if ConditionPassed() then EncodingSpecificOperations(); if !Halted() then if PSTATE.M IN {M32_User,M32_System} then UnpredictableProcedure(); // UNDEFINED or NOP else let new_pc_value : bits(32) = if PSTATE.EL == EL2 then ELR_hyp() else R(14); AArch32_ExceptionReturn(new_pc_value, SPSR_curr()); end; else // Perform DRPS operation in Debug state if PSTATE.M == M32_User then Undefined(); elsif PSTATE.M == M32_System then UnpredictableProcedure(); // UNDEFINED or NOP else SynchronizeContext(); DebugRestorePSR(); end; end; end;

CONSTRAINED UNPREDICTABLE behavior

If PSTATE.M IN {M32_User,M32_System}, then one of the following behaviors must occur:

Base Instructions
SIMD&FP Instructions
A32 Instructions by Encoding
T32 Instructions by Encoding
Shared Pseudocode
Proprietary Notice

2026-03_rel 2026-03-26 20:48:11

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