This is a collection of Intel®’ IA32® Software Developer's Manuals (URL of the day) and AMD' AMD64 Architecture Programmer's Manual together with the related specifications, application notes, white papers, and change logs. The collection aims to keep all available revisions. It was originally created by Michal Necasek, see OS/2 Museum.

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FSTMDBX, FSTMIAX

FSTMX stores multiple SIMD&FP registers from the Advanced SIMD and floating-point register file to consecutive locations in using an address from a general-purpose register.

Arm deprecates use of FSTMDBX and FSTMIAX, except for disassembly purposes, and reassembly of disassembled code.

Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For more information, see Enabling Advanced SIMD and floating-point support.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

Decode for all variants of this encoding

if P == '0' && U == '0' && W == '0' then See("Related encodings"); end; if P == '1' && W == '0' then See("VSTR"); end; if P == U && W == '1' then Undefined(); end; // Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !) let single_regs : boolean = FALSE; let add : boolean = (U == '1'); let wback : boolean = (W == '1'); let d : integer = UInt(D::Vd); let n : integer = UInt(Rn); let imm32 : bits(32) = ZeroExtend{}(imm8::'00'); let regs : integer = UInt(imm8) DIVRM 2; // If UInt(imm8) is odd, see "FSTDBMX, FSTMIAX". if n == 15 && (wback || CurrentInstrSet() != InstrSet_A32) then UnpredictableProcedure(); end; if regs == 0 || regs > 16 || (d+regs) > 32 then UnpredictableProcedure(); end; if imm8[0] == '1' && (d+regs) > 16 then UnpredictableProcedure(); end;

CONSTRAINED UNPREDICTABLE behavior

If regs == 0, then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The instruction operates as a VSTM with the same addressing mode but stores no registers.

If regs > 16 || (d+regs) > 16, then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The memory locations specified by the instruction and the number of registers specified by the instruction become UNKNOWN. If the instruction specifies writeback, then that register becomes UNKNOWN. This behavior does not affect any other memory locations.

T1

Decode for all variants of this encoding

if P == '0' && U == '0' && W == '0' then See("Related encodings"); end; if P == '1' && W == '0' then See("VSTR"); end; if P == U && W == '1' then Undefined(); end; // Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !) let single_regs : boolean = FALSE; let add : boolean = (U == '1'); let wback : boolean = (W == '1'); let d : integer = UInt(D::Vd); let n : integer = UInt(Rn); let imm32 : bits(32) = ZeroExtend{}(imm8::'00'); let regs : integer = UInt(imm8) DIVRM 2; // If UInt(imm8) is odd, see "FSTDBMX, FSTMIAX". if n == 15 && (wback || CurrentInstrSet() != InstrSet_A32) then UnpredictableProcedure(); end; if regs == 0 || regs > 16 || (d+regs) > 32 then UnpredictableProcedure(); end; if imm8[0] == '1' && (d+regs) > 16 then UnpredictableProcedure(); end;

CONSTRAINED UNPREDICTABLE behavior

If regs == 0, then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The instruction operates as a VSTM with the same addressing mode but stores no registers.

If regs > 16 || (d+regs) > 16, then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The memory locations specified by the instruction and the number of registers specified by the instruction become UNKNOWN. If the instruction specifies writeback, then that register becomes UNKNOWN. This behavior does not affect any other memory locations.

Assembler Symbols